Automatic test program generation for pipelined processors
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Test program generation for functional verification of PowerPC processors in IBM
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Efficient generation of counterexamples and witnesses in symbolic model checking
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Architecture validation for processors
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Formal verification of pipeline control using controlled token nets and abstract interpretation
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
EXPRESSION: a language for architecture exploration through compiler/simulator retargetability
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Micro architecture coverage directed generation of test programs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
High-level test generation for design verification of pipelined microprocessors
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Model checking
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Coverage directed test generation for functional verification using bayesian networks
Proceedings of the 40th annual Design Automation Conference
Computer Architecture: A Quantitative Approach
Computer Architecture: A Quantitative Approach
Using Counter Example Guided Abstraction Refinement to Find Complex Bugs
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Safety Property Verification Using Sequential SAT and Bounded Model Checking
IEEE Design & Test
Industrial experience with test generation languages for processor verification
Proceedings of the 41st annual Design Automation Conference
StressTest: an automatic approach to test generation via activity monitors
Proceedings of the 42nd annual Design Automation Conference
Functional Verification of Programmable Embedded Architectures: A Top-Down Approach
Functional Verification of Programmable Embedded Architectures: A Top-Down Approach
Test generation using SAT-based bounded model checking for validation of pipelined processors
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Specification-driven directed test generation for validation of pipelined processors
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Specification-based compaction of directed tests for functional validation of pipelined processors
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Processor Description Languages
Processor Description Languages
Functional test generation using design and property decomposition techniques
ACM Transactions on Embedded Computing Systems (TECS)
Integrated verification approach during ADL-driven processor design
Microelectronics Journal
Directed test generation for validation of multicore architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
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Functional validation is a major bottleneck in pipelined processor design. Simulation using functional test vectors is the most widely used form of processor validation. While existing model checking based approaches have proposed several promising ideas for efficient test generation, many challenges remain in applying them to realistic pipelined processors. The time and resources required for test generation using existing model checking based techniques can be extremely large. This paper presents an efficient test generation technique using decompositional model checking. The contribution of the paper is the development of both property and design decomposition procedures for efficient test generation of pipelined processors. Our experimental results using a multi-issue MIPS processor demonstrate several orders-of-magnitude reduction in memory requirement and test generation time.