The SPARC architecture manual: version 8
The SPARC architecture manual: version 8
Automatic test program generation for pipelined processors
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Test program generation for functional verification of PowerPC processors in IBM
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Efficient generation of counterexamples and witnesses in symbolic model checking
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Architecture validation for processors
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Formal verification of pipeline control using controlled token nets and abstract interpretation
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
EXPRESSION: a language for architecture exploration through compiler/simulator retargetability
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Micro architecture coverage directed generation of test programs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
High-level test generation for design verification of pipelined microprocessors
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Model checking
Functional abstraction driven design space exploration of heterogeneous programmable architectures
Proceedings of the 14th international symposium on Systems synthesis
Coverage Metrics for Functional Validation of Hardware Designs
IEEE Design & Test
Embedded Software-Based Self-Test for Programmable Core-Based Designs
IEEE Design & Test
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Coverage directed test generation for functional verification using bayesian networks
Proceedings of the 40th annual Design Automation Conference
Combining ATPG and Symbolic Simulation for Efficient Validation of Embedded Array Systems
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Using Model Checking to Generate Tests from Specifications
ICFEM '98 Proceedings of the Second IEEE International Conference on Formal Engineering Methods
Computer Architecture: A Quantitative Approach
Computer Architecture: A Quantitative Approach
Synthesis-driven Exploration of Pipelined Embedded Processors
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Using Counter Example Guided Abstraction Refinement to Find Complex Bugs
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Graph-Based Functional Test Program Generation for Pipelined Processors
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Safety Property Verification Using Sequential SAT and Bounded Model Checking
IEEE Design & Test
Functional Coverage Driven Test Generation for Validation of Pipelined Processors
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
StressTest: an automatic approach to test generation via activity monitors
Proceedings of the 42nd annual Design Automation Conference
Test generation using SAT-based bounded model checking for validation of pipelined processors
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Functional test generation using property decompositions for validation of pipelined processors
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study
MTV '06 Proceedings of the Seventh International Workshop on Microprocessor Test and Verification
Test Generation for Microprocessors
IEEE Transactions on Computers
Functional Verification Coverage Measurement and Analysis
Functional Verification Coverage Measurement and Analysis
Specification-based compaction of directed tests for functional validation of pipelined processors
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Generating test programs to cover pipeline interactions
Proceedings of the 46th Annual Design Automation Conference
Functional test generation using efficient property clustering and learning techniques
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Automatic RTL Test Generation from SystemC TLM Specifications
ACM Transactions on Embedded Computing Systems (TECS)
Automated generation of directed tests for transition coverage in cache coherence protocols
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
A novel approach for implementing microarchitectural verification plans in processor designs
HVC'12 Proceedings of the 8th international conference on Hardware and Software: verification and testing
Extensible environment for test program generation for microprocessors
Programming and Computing Software
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Functional validation is a major bottleneck in pipelined processor design due to the combined effects of increasing design complexity and lack of efficient techniques for directed test generation. Directed test vectors can reduce overall validation effort, since shorter tests can obtain the same coverage goal compared to the random tests. This article presents a specification-driven directed test generation methodology. The proposed methodology makes three important contributions. First, a general graph model is developed that can capture the structure and behavior (instruction set) of a wide variety of pipelined processors. The graph model is generated from the processor specification. Next, we propose a functional fault model that is used to define the functional coverage for pipelined architectures. Finally, we propose two complementary test generation techniques: test generation using model checking, and test generation using template-based procedures. These test generation techniques accept the graph model of the architecture as input and generate test programs to detect all the faults in the functional fault model. Our experimental results on two pipelined processor models demonstrate several orders-of-magnitude reduction in overall validation effort by drastically reducing both test-generation time and number of test programs required to achieve a coverage goal.