Coverage directed test generation for functional verification using bayesian networks
Proceedings of the 40th annual Design Automation Conference
MicroGP—An Evolutionary Assembly Program Generator
Genetic Programming and Evolvable Machines
Piparazzi: a test program generator for micro-architecture flow verification
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
Comprehensive Functional Verification: The Complete Industry Cycle (Systems on Silicon)
Comprehensive Functional Verification: The Complete Industry Cycle (Systems on Silicon)
Specification-driven directed test generation for validation of pipelined processors
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Towards Automating Simulation-Based Design Verification Using ILP
Inductive Logic Programming
Feedback-based coverage directed test generation: an industrial evaluation
HVC'10 Proceedings of the 6th international conference on Hardware and software: verification and testing
Advances in simultaneous multithreading testcase generation methods
HVC'10 Proceedings of the 6th international conference on Hardware and software: verification and testing
Learning microarchitectural behaviors to improve stimuli generation quality
Proceedings of the 48th Design Automation Conference
Microprocessor Verification via Feedback-Adjusted Markov Models
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Generating instruction streams using abstract CSP
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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The ever-growing microarchitecture complexity of processors creates a widening gap between the verification plan and the test generation technologies used in its implementation. This gap impacts the cost and quality of the verification process. To overcome this, we introduce a novel test generation platform for processor verification. This approach is based on a scenario description language that is close to the microarchitecture verification plan, and uses new test generation algorithms and a microarchitectural model to support this higher level of abstraction. Initial results on a high end industrial design show our approach reduces the effort of implementing a microarchitectural verification plan and improves the quality of verification.