Elements of information theory
Elements of information theory
C4.5: programs for machine learning
C4.5: programs for machine learning
Coverage directed test generation for functional verification using bayesian networks
Proceedings of the 40th annual Design Automation Conference
MicroGP—An Evolutionary Assembly Program Generator
Genetic Programming and Evolvable Machines
Comprehensive Functional Verification: The Complete Industry Cycle (Systems on Silicon)
Comprehensive Functional Verification: The Complete Industry Cycle (Systems on Silicon)
Towards Automating Simulation-Based Design Verification Using ILP
Inductive Logic Programming
Microprocessor Verification via Feedback-Adjusted Markov Models
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Novel test detection to improve simulation efficiency: a commercial experiment
Proceedings of the International Conference on Computer-Aided Design
Simulation knowledge extraction and reuse in constrained random processor verification
Proceedings of the 50th Annual Design Automation Conference
A novel approach for implementing microarchitectural verification plans in processor designs
HVC'12 Proceedings of the 8th international conference on Hardware and Software: verification and testing
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Microarchitectural information regarding various aspects of instruction execution can help processor-level stimuli generators more easily reach verification goals. While many such aspects are based on common microarchitectural concepts, their specific manifestations are highly design-specific. We propose using an automatic method for acquiring such microarchitectural knowledge and integrating it into the stimuli generator. We start by extracting microarchitectural data from simulation traces. This data is fed to a decision tree learning algorithm that produces rules for microarchitectural behavior of instructions; these rules are then integrated into the testing knowledge of the stimuli generator. This testing knowledge can provide users with the ability to better control the microarchitectural behavior of generated instructions, leading to higher quality test cases. Experimental results on the POWER7 processor showed that our proposed method can improve the microarchitectural coverage of the design.