Industrial experience with test generation languages for processor verification
Proceedings of the 41st annual Design Automation Conference
Generating concurrent test-programs with collisions for multi-processor verification
HLDVT '02 Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop
Functional verification of the POWER5 microprocessor and POWER5 multiprocessor systems
IBM Journal of Research and Development - POWER5 and packaging
Introduction to the cell multiprocessor
IBM Journal of Research and Development - POWER5 and packaging
IBM Journal of Research and Development
Post-silicon validation opportunities, challenges and recent advances
Proceedings of the 47th Design Automation Conference
Hazard driven test generation for SMT processors
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Leveraging accelerated simulation for floating-point regression
HVC'12 Proceedings of the 8th international conference on Hardware and Software: verification and testing
A novel approach for implementing microarchitectural verification plans in processor designs
HVC'12 Proceedings of the 8th international conference on Hardware and Software: verification and testing
| Hi-index | 0.00 |
Many modern microprocessor architectures utilize simultaneous multithreading (SMT) for increased performance. This trend is exemplified in IBM's Power series of high-end microprocessors which steadily increased the number of threads in a system in its POWER5, POWER6 and POWER7 designs. In this paper we discuss the steady increase in functional verification complexity introduced by each of these designs and the corresponding improvements to SMT verification methods that were necessary in order to cope with the growing verification challenge. We review three different verification technologies which were specifically developed to target SMT aspects of processor designs, and compare their relative advantages and drawbacks. Our focus is on the novel Thread Irritation technique - we demonstrate its effectiveness in finding high quality SMT bugs early in the verification cycle, and show how it was adopted to the post-silicon platform.