Hazard driven test generation for SMT processors

Authors:
Padmaraj Singh;Vijaykrishnan Narayanan;David L. Landis
Affiliations:
Nvidia, Portland, OR;Pennsylvania State University, University Park, PA;Carnegie Mellon University, Pittsburgh, PA
Venue:
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Year:
2012

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Abstract

Multithreaded processors increase throughput by executing multiple independent programs on a single pipeline. Simultaneous Multithreaded (SMT) processors execute multiple threads simultaneously thus add a significant dimension to the design complexity. Dealing with this complexity calls for extended and innovative design verification efforts. This paper develops an analytic model based SMT random test generation technique. SMT analytic model parameters are applied to create random tests with high utilization and increased contention. To demonstrate the methodology, parameters extracted from the PPC ISA and sample processor configurations are simulated on the SMT analytic model. The methodology focuses on exploiting data/control and structural hazards to guide the random test generator to create effective SMT tests.