Enhanced Equivalence Checking: Toward a Solidarity of Functional Verification and Manufacturing Test Generation

Authors:
Jayanta Bhadra;Narayanan Krishnamurthy;Magdy S. Abadir
Affiliations:
Freescale Semiconductor;Freescale Semiconductor;Freescale Semiconductor
Venue:
IEEE Design & Test
Year:
2004

Citing 5
Cited 1

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Abstract

Editor's note: This article, from the Motorola (now Freescale) PowerPC design group, presents an interesting synergy among test, equivalence verification, and constraints. The authors use RTL, gate, and switch models of a design in two different flows驴one for test and one for functional verification驴to show that rectifying constraints and merging tests between the two flows saves significant presilicon debug effort.