Architecture validation for processors
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Automatic generation of functional vectors using the extended finite state machine model
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Abstraction Techniques for Validation Coverage Analysis and Test Generation
IEEE Transactions on Computers
Efficient Techniques for Dynamic Test Sequence Compaction
IEEE Transactions on Computers
High-level test generation for design verification of pipelined microprocessors
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
An RTL Abstraction Technique for Processor MicroarchitectureValidation and Test Generation
Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Effectiveness of Microarchitecture Test Program Generation
IEEE Design & Test
Test vector decomposition-based static compaction algorithms for combinational circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Functional test generation using property decompositions for validation of pipelined processors
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Verification of the cell broadband engine™ processor
Proceedings of the 43rd annual Design Automation Conference
Specification-driven directed test generation for validation of pipelined processors
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Processor Description Languages
Processor Description Languages
Using model-based test program generator for simulation validation
ICESS'04 Proceedings of the First international conference on Embedded Software and Systems
An optimal test compression procedure for combinational circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Explicit and implicit algorithms for binate covering problems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Functional test generation using efficient property clustering and learning techniques
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test compaction techniques for assertion-based test generation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Functional validation is a major bottleneck in microprocessor design methodology. Simulation is the widely used method for functional validation using billions of random and biased-random test programs. Although directed tests require a smaller test set compared to random tests to achieve the same functional coverage goal, there is a lack of automated techniques for directed test generation. Furthermore, the number of directed tests can still be prohibitively large. This paper presents a methodology for specification-based coverage analysis and test generation. The primary contribution of this paper is a compaction technique that can drastically reduce the required number of directed test programs to achieve a coverage goal. Our experimental results using a MIPS processor and an industrial processor (e500) demonstrate more than 90% reduction in number of directed tests without sacrificing the functional coverage goal.