Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Formal hardware verification by symbolic ternary trajectory evaluation
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Automatic test program generation for pipelined processors
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Formally verifying a microprocessor using a simulation methodology
DAC '94 Proceedings of the 31st annual Design Automation Conference
Architecture validation for processors
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Formal verification of a superscalar execution unit
DAC '97 Proceedings of the 34th annual Design Automation Conference
Abstraction Techniques for Validation Coverage Analysis and Test Generation
IEEE Transactions on Computers
A Buffer-Oriented Methodology for Microarchitecture Validation
Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification
An RTL Abstraction Technique for Processor MicroarchitectureValidation and Test Generation
Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification
Symbolic Model Checking
Formal Verification of Hardware Design
Formal Verification of Hardware Design
Switching and Finite Automata Theory: Computer Science Series
Switching and Finite Automata Theory: Computer Science Series
Coverage-Directed Test Generation Using Symbolic Techniques
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
Automatic verification of Pipelined Microprocessor Control
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
Superscalar Processor Validation at the Microarchitecture Level
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
Specification-based compaction of directed tests for functional validation of pipelined processors
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Functional test generation using design and property decomposition techniques
ACM Transactions on Embedded Computing Systems (TECS)
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The effectiveness of microarchitecture test program generation (MTPG) within the buffer-oriented microarchitecture validation (BMV) methodology is presented. A list of design errors typically encountered in industry is investigated to determine if our microarchitecture test programs can detect them. Two metrics are used to determine design error coverage: Functional deviation ( f ) is the discrepancy in coverage of our microarchitecture model when simulating the incorrect and error-free designs. Timing deviation ( t) is the discrepancy in the number of cycles needed to simulate a test program between the incorrect and error-free designs. Simulation results show that our test programs detect over 98% of the design errors based on the two detection metrics used.