Analysis of discrete event coordination
REX workshop Proceedings on Stepwise refinement of distributed systems: models, formalisms, correctness
Sequential circuit verification using symbolic model checking
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Formal hardware verification by symbolic ternary trajectory evaluation
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
The PowerPC architecture: a specification for a new family of RISC processors
The PowerPC architecture: a specification for a new family of RISC processors
Computer-aided verification of coordinating processes: the automata-theoretic approach
Computer-aided verification of coordinating processes: the automata-theoretic approach
Formally verifying a microprocessor using a simulation methodology
DAC '94 Proceedings of the 31st annual Design Automation Conference
Formal verification by symbolic evaluation of partially-ordered trajectories
Formal Methods in System Design - Special issue on symbolic model checking
IEEE Spectrum
RuleBase: an industry-oriented formal verification tool
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Inside the as/400
Symbolic Model Checking
Verifying Nondeterministic Implementations of Deterministic Systems
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
A Buffer-Oriented Methodology for Microarchitecture Validation
Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification
Effectiveness of Microarchitecture Test Program Generation
IEEE Design & Test
TABLEAUX '99 Proceedings of the International Conference on Automated Reasoning with Analytic Tableaux and Related Methods
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Efficient Generation of Monitor Circuits for GSTE Assertion Graphs
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Maximal models of assertion graph in GSTE
TAMC'06 Proceedings of the Third international conference on Theory and Applications of Models of Computation
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Many modern systems are designed as a set of interconnectedreactive subsystems. The subsystem verification task is toverify an implementation of the subsystem against the simple deterministichigh-level specification of the entire system. Our verificationmethodology, based on Symbolic Trajectory Evaluation, is ableto bridge the wide gap between the abstract specification and theimplementation specific details of the subsystem. This paper presentsa detailed description of an industrial application of this methodologyto the fixed point execution unit of the PowerPC processor.We were able to verify a representative instruction under all possiblestall, bypass, pipeline conditions and under all possible timingsfor interface to other functional units in the processor.