Specification and verification of concurrent programs by A∀automata
POPL '87 Proceedings of the 14th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Symbolic model checking: 1020 states and beyond
Information and Computation - Special issue: Selections from 1990 IEEE symposium on logic in computer science
High-level symbolic construction technique for high performance sequential synthesis
DAC '93 Proceedings of the 30th international Design Automation Conference
Computer-aided verification of coordinating processes: the automata-theoretic approach
Computer-aided verification of coordinating processes: the automata-theoretic approach
Formal verification by symbolic evaluation of partially-ordered trajectories
Formal Methods in System Design - Special issue on symbolic model checking
Formal verification of PowerPC arrays using symbolic trajectory evaluation
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Formal verification of a superscalar execution unit
DAC '97 Proceedings of the 34th annual Design Automation Conference
Combining theorem proving and trajectory evaluation in an industrial environment
DAC '98 Proceedings of the 35th annual Design Automation Conference
Principles of verifiable RTL design: a functional coding style supporting verification processes in Verilog
Modeling design constraints and biasing in simulation using BDDs
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
High-Level specification and automatic generation of IP interface monitors
Proceedings of the 39th annual Design Automation Conference
Monitor-Based Formal Specification of PCI
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Generalized Symbolic Trajectory Evaluation - Abstraction in Action
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Recognizing Regular Expressions by Means of Dataflow Networks
ICALP '96 Proceedings of the 23rd International Colloquium on Automata, Languages and Programming
Specification and verification of concurrent systems in CESAR
Proceedings of the 5th Colloquium on International Symposium on Programming
Design Constraints in Symbolic Model Checking
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic
Logic of Programs, Workshop
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Compositional verification of an ATM switch module using interface recognizer/suppliers (IRS)
HLDVT '00 Proceedings of the IEEE International High-Level Validation and Test Workshop (HLDVT'00)
Introduction to Generalized Symbolic Trajectory Evaluation
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
High level validation of next-generation microprocessors
HLDVT '02 Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop
Implication of assertion graphs in GSTE
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
An assertion-based verification methodology for system-level design
Computers and Electrical Engineering
BackSpace: formal analysis for post-silicon debug
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Maximal models of assertion graph in GSTE
TAMC'06 Proceedings of the Third international conference on Theory and Applications of Models of Computation
Post-silicon conformance checking with virtual prototypes
Proceedings of the 50th Annual Design Automation Conference
Formal-analysis-based trace computation for post-silicon debug
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Generalized symbolic trajectory evaluation (GSTE) is a powerful,new method for formal verification that combines the industrially-provenscalability and capacity of classical symbolic trajectoryevaluation with the expressive power of temporal-logic modelchecking. GSTE was originally developed at Intel and hasbeen used successfully on Intel's next-generation microprocessors.However, the supporting algorithms and tools for GSTE are stillrelatively immature.GSTE specifications are given as assertion graphs, an extensionof 驴-automata. This paper presents a linear-time, linear-size translationfrom GSTE assertion graphs into monitor circuits, which canbe used with dynamic verification both as a quick "sanity check" ofthe specification before effort is invested in abstraction and formalverification, and also as means to reuse GSTE specifications withother validations methods. We present experimental results usingreal GSTE assertion graphs for real industrial circuits, showing thatthe circuit construction procedure is efficient in practice and that themonitor circuits impose minimal simulation overhead.