Principles of verifiable RTL design: a functional coding style supporting verification processes in Verilog

RTL-Based Functional Test Generation for High Defects Coverage in Digital Systems

Journal of Electronic Testing: Theory and Applications

Optimizing Multiple EDA Tools within the ASIC Design Flow

IEEE Design & Test

PROSPER - An Investigation into Software Architecture for Embedded Proof Engines

FroCoS '02 Proceedings of the 4th International Workshop on Frontiers of Combining Systems

Efficient Generation of Monitor Circuits for GSTE Assertion Graphs

Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design

Symbolic simulation of industrial real-time and embedded systems -experiments with the bluetooth baseband communication protocol

Journal of Embedded Computing - Real-Time and Embedded Computing Systems

Vacuity in testing

TAP'08 Proceedings of the 2nd international conference on Tests and proofs

Coverage in interpolation-based model checking

Proceedings of the 47th Design Automation Conference

Sanity checks in formal verification

CONCUR'06 Proceedings of the 17th international conference on Concurrency Theory