A two-state methodology for RTL logic simulation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Model checking
Principles of verifiable RTL design: a functional coding style supporting verification processes in Verilog
On the criteria to be used in decomposing systems into modules
Communications of the ACM
An ALGOL-like computer design language
Communications of the ACM
IEEE Standard Description Language Based on the VERILOG Hardware Description Language, 1364-1995
IEEE Standard Description Language Based on the VERILOG Hardware Description Language, 1364-1995
Formal Equivalence Checking and Design DeBugging
Formal Equivalence Checking and Design DeBugging
Digital Systems: Hardware Organization and Design
Digital Systems: Hardware Organization and Design
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This proposed design methodology incorporates modern programming language principles, such as information hiding, to let engineers optimize a design's functionality and simultaneously support multiple EDA tools.