Reasoning about infinite computations
Information and Computation
Formally verifying a microprocessor using a simulation methodology
DAC '94 Proceedings of the 31st annual Design Automation Conference
Software unit test coverage and adequacy
ACM Computing Surveys (CSUR)
What's between simulation and formal verification? (extended abstract)
DAC '98 Proceedings of the 35th annual Design Automation Conference
Coverage estimation for symbolic model checking
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Model checking
Principles of verifiable RTL design: a functional coding style supporting verification processes in Verilog
Efficient Detection of Vacuity in Temporal Model Checking
Formal Methods in System Design - Special issue on CAV '97
Model Checking of Safety Properties
Formal Methods in System Design
Coverage Metrics for Functional Validation of Hardware Designs
IEEE Design & Test
Coverage Metrics for Temporal Logic Model Checking
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Coverage of Implementations by Simulating Specifications
TCS '02 Proceedings of the IFIP 17th World Computer Congress - TC1 Stream / 2nd IFIP International Conference on Theoretical Computer Science: Foundations of Information Technology in the Era of Networking and Mobile Computing
Efficient monitoring of safety properties
International Journal on Software Tools for Technology Transfer (STTT) - Special section on tools and algorithms for the construction and analysis of systems
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Defining and Providing Coverage for Assertion-Based Dynamic Verification
Journal of Electronic Testing: Theory and Applications
Towards a notion of unsatisfiable and unrealizable cores for LTL
Science of Computer Programming
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In recent years, we see a growing awareness to the importance of assessing the quality of specifications. In the context of model checking, this can be done by analyzing the effect of applying mutations to the specification or the system. If the system satisfies the mutated specification, we know that some elements of the specification do not play a role in its satisfaction, thus the specification is satisfied in some vacuous way. If the mutated system satisfies the specification, we know that some elements of the system are not covered by the specification. Coverage in model checking has been adopted from the area of testing, where coverage information is crucial in measuring the exhaustiveness of test suits. It is now time for model checking to pay back, and let testing enjoy the rich theory and applications of vacuity. We define and study vacuous satisfaction in the context of testing, and demonstrate how vacuity analysis can lead to better specifications and test suits.