The complexity of propositional linear temporal logics
Journal of the ACM (JACM)
A Structure-preserving Clause Form Translation
Journal of Symbolic Computation
On the synthesis of a reactive module
POPL '89 Proceedings of the 16th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
On the development of reactive systems
Logics and models of concurrent systems
Handbook of theoretical computer science (vol. B)
An optimality result for clause form translation
Journal of Symbolic Computation
ACM Transactions on Programming Languages and Systems (TOPLAS)
Symbolic model checking: 1020 states and beyond
Information and Computation - Special issue: Selections from 1990 IEEE symposium on logic in computer science
Formally verifying a microprocessor using a simulation methodology
DAC '94 Proceedings of the 31st annual Design Automation Conference
Symbolic model checking using SAT procedures instead of BDDs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Checking that finite state concurrent programs satisfy their linear specification
POPL '85 Proceedings of the 12th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Model checking
Synthesis of Communicating Processes from Temporal Logic Specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
Practically useful variants of definitional translations to normal form
Information and Computation
ACM Transactions on Computational Logic (TOCL)
Efficient Detection of Vacuity in Temporal Model Checking
Formal Methods in System Design - Special issue on CAV '97
Automata on Infinite Objects and Church's Problem
Automata on Infinite Objects and Church's Problem
Another Look at LTL Model Checking
Formal Methods in System Design
Simple on-the-fly automatic verification of linear temporal logic
Proceedings of the Fifteenth IFIP WG6.1 International Symposium on Protocol Specification, Testing and Verification XV
Realizable and Unrealizable Specifications of Reactive Systems
ICALP '89 Proceedings of the 16th International Colloquium on Automata, Languages and Programming
Checking Safety Properties Using Induction and a SAT-Solver
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
A Fixpoint Based Encoding for Bounded Model Checking
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
The LPSAT Engine & Its Application to Resource Planning
IJCAI '99 Proceedings of the Sixteenth International Joint Conference on Artificial Intelligence
Symbolic Model Checking without BDDs
TACAS '99 Proceedings of the 5th International Conference on Tools and Algorithms for Construction and Analysis of Systems
From Falsification to Verification
FST TCS '01 Proceedings of the 21st Conference on Foundations of Software Technology and Theoretical Computer Science
Specification and verification of concurrent systems in CESAR
Proceedings of the 5th Colloquium on International Symposium on Programming
Improved Automata Generation for Linear Temporal Logic
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
Verifiying Safety Properties of a Power PC Microprocessor Using Symbolic Model Checking without BDDs
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic
Logic of Programs, Workshop
Deterministic generators and games for Ltl fragments
ACM Transactions on Computational Logic (TOCL)
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Verification of Proofs of Unsatisfiability for CNF Formulas
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
FOCS '05 Proceedings of the 46th Annual IEEE Symposium on Foundations of Computer Science
Formal analysis of hardware requirements
Proceedings of the 43rd annual Design Automation Conference
Coverage metrics for temporal logic model checking
Formal Methods in System Design
Optimizations for LTL Synthesis
FMCAD '06 Proceedings of the Formal Methods in Computer Aided Design
Interactive presentation: Automatic hardware synthesis from specifications: a case study
Proceedings of the conference on Design, automation and test in Europe
Specify, Compile, Run: Hardware from PSL
Electronic Notes in Theoretical Computer Science (ENTCS)
Exploiting Resolution Proofs to Speed Up LTL Vacuity Detection for BMC
FMCAD '07 Proceedings of the Formal Methods in Computer Aided Design
Easier and More Informative Vacuity Checks
MEMOCODE '07 Proceedings of the 5th IEEE/ACM International Conference on Formal Methods and Models for Codesign
Principles of Model Checking (Representation and Mind Series)
Principles of Model Checking (Representation and Mind Series)
The temporal logic of programs
SFCS '77 Proceedings of the 18th Annual Symposium on Foundations of Computer Science
The complexity of facets resolved
SFCS '85 Proceedings of the 26th Annual Symposium on Foundations of Computer Science
On the complexity of omega -automata
SFCS '88 Proceedings of the 29th Annual Symposium on Foundations of Computer Science
Finding Minimal Unsatisfiable Cores of Declarative Specifications
FM '08 Proceedings of the 15th international symposium on Formal Methods
ICALP '08 Proceedings of the 35th international colloquium on Automata, Languages and Programming, Part II
Object Models with Temporal Constraints
SEFM '08 Proceedings of the 2008 Sixth IEEE International Conference on Software Engineering and Formal Methods
Formal Methods in System Design
Beyond vacuity: towards the strongest passing formula
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Compositional Synthesis of Reactive Systems from Live Sequence Chart Specifications
TACAS '09 Proceedings of the 15th International Conference on Tools and Algorithms for the Construction and Analysis of Systems: Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2009,
Controller Synthesis from LSC Requirements
FASE '09 Proceedings of the 12th International Conference on Fundamental Approaches to Software Engineering: Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2009
A Framework for Inherent Vacuity
HVC '08 Proceedings of the 4th International Haifa Verification Conference on Hardware and Software: Verification and Testing
Requirements Validation for Hybrid Systems
CAV '09 Proceedings of the 21st International Conference on Computer Aided Verification
From Informal Requirements to Property-Driven Formal Validation
Formal Methods for Industrial Critical Systems
Diagnosing and solving over-determined constraint satisfaction problems
IJCAI'93 Proceedings of the 13th international joint conference on Artifical intelligence - Volume 1
Non-standard reasoning services for the debugging of description logic terminologies
IJCAI'03 Proceedings of the 18th international joint conference on Artificial intelligence
A resolution method for temporal logic
IJCAI'91 Proceedings of the 12th international joint conference on Artificial intelligence - Volume 1
Resolution-Based Model Construction for PLTL
TIME '09 Proceedings of the 2009 16th International Symposium on Temporal Representation and Reasoning
A constraint solver for software engineering: finding models and cores of large relational specifications
Supporting Requirements Validation: The EuRailCheck Tool
ASE '09 Proceedings of the 2009 IEEE/ACM International Conference on Automated Software Engineering
A simple and flexible way of computing small unsatisfiable cores in SAT modulo theories
SAT'07 Proceedings of the 10th international conference on Theory and applications of satisfiability testing
RAT: a tool for the formal analysis of requirements
CAV'07 Proceedings of the 19th international conference on Computer aided verification
Boolean abstraction for temporal logic satisfiability
CAV'07 Proceedings of the 19th international conference on Computer aided verification
MUST: provide a finer-grained explanation of unsatisfiability
CP'07 Proceedings of the 13th international conference on Principles and practice of constraint programming
On the notion of vacuous truth
LPAR'07 Proceedings of the 14th international conference on Logic for programming, artificial intelligence and reasoning
Diagnostic information for realizability
VMCAI'08 Proceedings of the 9th international conference on Verification, model checking, and abstract interpretation
A hybrid algorithm for LTL games
VMCAI'08 Proceedings of the 9th international conference on Verification, model checking, and abstract interpretation
Antichains: alternative algorithms for LTL satisfiability and model-checking
TACAS'08/ETAPS'08 Proceedings of the Theory and practice of software, 14th international conference on Tools and algorithms for the construction and analysis of systems
TAP'08 Proceedings of the 2nd international conference on Tests and proofs
Formalization and validation of a subset of the European Train Control System
Proceedings of the 32nd ACM/IEEE International Conference on Software Engineering - Volume 2
International Journal on Software Tools for Technology Transfer (STTT) - Special Section on SPIN 07
Debugging OWL-DL ontologies: a heuristic approach
ISWC'05 Proceedings of the 4th international conference on The Semantic Web
Towards a notion of unsatisfiable cores for LTL
FSEN'09 Proceedings of the Third IPM international conference on Fundamentals of Software Engineering
RATSY – a new requirements analysis tool with synthesis
CAV'10 Proceedings of the 22nd international conference on Computer Aided Verification
Synthesis of reactive(1) designs
VMCAI'06 Proceedings of the 7th international conference on Verification, Model Checking, and Abstract Interpretation
Incremental and complete bounded model checking for full PLTL
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
A scalable algorithm for minimal unsatisfiable core extraction
SAT'06 Proceedings of the 9th international conference on Theory and Applications of Satisfiability Testing
Evaluating LTL satisfiability solvers
ATVA'11 Proceedings of the 9th international conference on Automated technology for verification and analysis
Proving and explaining the unfeasibility of message sequence charts for hybrid systems
Proceedings of the International Conference on Formal Methods in Computer-Aided Design
Behavioral diagnosis of LTL specifications at operator level
IJCAI'13 Proceedings of the Twenty-Third international joint conference on Artificial Intelligence
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Unsatisfiable cores, i.e., parts of an unsatisfiable formula that are themselves unsatisfiable, have important uses in debugging specifications, speeding up search in model checking or SMT, and generating certificates of unsatisfiability. While unsatisfiable cores have been well investigated for Boolean SAT and constraint programming, the notion of unsatisfiable cores for temporal logics such as LTL has not received much attention. In this paper we investigate notions of unsatisfiable cores for LTL that arise from the syntax tree of an LTL formula, from converting it into a conjunctive normal form, and from proofs of its unsatisfiability. The resulting notions are more fine-grained than existing ones. We illustrate the benefits of the more fine-grained notions on examples from the literature. We extend some of the notions to realizability and we discuss the relationship of unsatisfiable and unrealizable cores with the notion of vacuity.