Interactive presentation: Automatic hardware synthesis from specifications: a case study
Proceedings of the conference on Design, automation and test in Europe
Specify, Compile, Run: Hardware from PSL
Electronic Notes in Theoretical Computer Science (ENTCS)
Avida-MDE: a digital evolution approach to generating models of adaptive software behavior
Proceedings of the 10th annual conference on Genetic and evolutionary computation
ICALP '08 Proceedings of the 35th international colloquium on Automata, Languages and Programming, Part II
Environment Assumptions for Synthesis
CONCUR '08 Proceedings of the 19th international conference on Concurrency Theory
Automatically Generating Behavioral Models of Adaptive Systems to Address Uncertainty
MoDELS '08 Proceedings of the 11th international conference on Model Driven Engineering Languages and Systems
Compositional Synthesis of Reactive Systems from Live Sequence Chart Specifications
TACAS '09 Proceedings of the 15th International Conference on Tools and Algorithms for the Construction and Analysis of Systems: Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2009,
An Antichain Algorithm for LTL Realizability
CAV '09 Proceedings of the 21st International Conference on Computer Aided Verification
From program verification to program synthesis
Proceedings of the 37th annual ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Automated composition of Web services via planning in asynchronous domains
Artificial Intelligence
A hybrid algorithm for LTL games
VMCAI'08 Proceedings of the 9th international conference on Verification, model checking, and abstract interpretation
PLDI '10 Proceedings of the 2010 ACM SIGPLAN conference on Programming language design and implementation
Automated composition of nondeterministic stateful services
WS-FM'09 Proceedings of the 6th international conference on Web services and formal methods
Compositional algorithms for LTL synthesis
ATVA'10 Proceedings of the 8th international conference on Automated technology for verification and analysis
Debugging unrealizable specifications with model-based diagnosis
HVC'10 Proceedings of the 6th international conference on Hardware and software: verification and testing
Synthesis for regular specifications over unbounded domains
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
Efficiently solving quantified bit-vector formulas
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
Antichains and compositional algorithms for LTL synthesis
Formal Methods in System Design
Journal of Computer and System Sciences
CAV'10 Proceedings of the 22nd international conference on Computer Aided Verification
RATSY – a new requirements analysis tool with synthesis
CAV'10 Proceedings of the 22nd international conference on Computer Aided Verification
Synthesis of Reactive(1) designs
Journal of Computer and System Sciences
Towards a notion of unsatisfiable and unrealizable cores for LTL
Science of Computer Programming
Formal Methods in System Design
Synthesis for unbounded bit-vector arithmetic
IJCAR'12 Proceedings of the 6th international joint conference on Automated Reasoning
Deterministic automata for the (f, g)-fragment of LTL
CAV'12 Proceedings of the 24th international conference on Computer Aided Verification
Acacia+, a tool for LTL synthesis
CAV'12 Proceedings of the 24th international conference on Computer Aided Verification
MGSyn: automatic synthesis for industrial automation
CAV'12 Proceedings of the 24th international conference on Computer Aided Verification
Generalized reactivity(1) synthesis without a monolithic strategy
HVC'11 Proceedings of the 7th international Haifa Verification conference on Hardware and Software: verification and testing
Efficiently solving quantified bit-vector formulas
Formal Methods in System Design
Automatic behavior composition synthesis
Artificial Intelligence
Synthesis from LTL specifications with mean-payoff objectives
TACAS'13 Proceedings of the 19th international conference on Tools and Algorithms for the Construction and Analysis of Systems
SAT: Based bounded strong satisfiability checking of reactive system specifications
ICT-EurAsia'13 Proceedings of the 2013 international conference on Information and Communication Technology
Fair Synthesis for Asynchronous Distributed Systems
ACM Transactions on Computational Logic (TOCL)
Synthesis modulo recursive functions
Proceedings of the 2013 ACM SIGPLAN international conference on Object oriented programming systems languages & applications
Automatic generation of quality specifications
CAV'13 Proceedings of the 25th international conference on Computer Aided Verification
Automata with generalized rabin pairs for probabilistic model checking and LTL synthesis
CAV'13 Proceedings of the 25th international conference on Computer Aided Verification
PARTY: parameterized synthesis of token rings
CAV'13 Proceedings of the 25th international conference on Computer Aided Verification
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We present an approach to automatic synthesis of specifications given in Linear Time Logic. The approach is based on a translation through universal co-Büchi tree automata and alternating weak tree automata [1]. By careful optimization of all intermediate automata, we achieve a major improvement in performance. We present several optimization techniques for alternating tree automata, including a game-based approximation to language emptiness and a simulation-based optimization. Furthermore, we use an incremental algorithm to compute the emptiness of nondeterministic Büchi tree automata. All our optimizations are computed in time polynomial in the size of the automaton on which they are computed. We have applied our implementation to several examples and show a significant improvement over the straightforward implementation. Although our examples are still small, this work constitutes the first implementation of a synthesis algorithm for full LTL. We believe that the optimizations discussed here form an important step towards making LTL synthesis practical.