Generalized reactivity(1) synthesis without a monolithic strategy

Authors:
Matthias Schlaipfer;Georg Hofferek;Roderick Bloem
Affiliations:
Institute for Applied Information Processing and Communications (IAIK), Graz University of Technology, Austria;Institute for Applied Information Processing and Communications (IAIK), Graz University of Technology, Austria;Institute for Applied Information Processing and Communications (IAIK), Graz University of Technology, Austria
Venue:
HVC'11 Proceedings of the 7th international Haifa Verification conference on Hardware and Software: verification and testing
Year:
2011

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Abstract

We present a new approach to synthesizing systems from Generalized Reactivity(1) specifications. Our method does not require a monolithic strategy, which can be prohibitively large. Instead, our approach constructs a circuit directly from the iterates of the fixpoint computation that computes the winning region. We build the overall system by combining these circuit parts. Our approach has generally lower memory requirements than previous GR(1) synthesis approaches, and is also faster. In addition to that, the circuits we build are eager, in the sense that they typically fulfill system guarantees faster than the circuits obtained with previous approaches, as experiments show.