Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Synthesizing Distributed Systems
LICS '01 Proceedings of the 16th Annual IEEE Symposium on Logic in Computer Science
LICS '05 Proceedings of the 20th Annual IEEE Symposium on Logic in Computer Science
FOCS '05 Proceedings of the 46th Annual IEEE Symposium on Foundations of Computer Science
From Nondeterministic Buchi and Streett Automata to Deterministic Parity Automata
LICS '06 Proceedings of the 21st Annual IEEE Symposium on Logic in Computer Science
Distributed reactive systems are hard to synthesize
SFCS '90 Proceedings of the 31st Annual Symposium on Foundations of Computer Science
SMT-based synthesis of distributed systems
Proceedings of the second workshop on Automated formal methods
ATL* Satisfiability Is 2EXPTIME-Complete
ICALP '08 Proceedings of the 35th international colloquium on Automata, Languages and Programming, Part II
Safraless procedures for timed specifications
FORMATS'10 Proceedings of the 8th international conference on Formal modeling and analysis of timed systems
Compositional algorithms for LTL synthesis
ATVA'10 Proceedings of the 8th international conference on Automated technology for verification and analysis
Unbeast: symbolic bounded synthesis
TACAS'11/ETAPS'11 Proceedings of the 17th international conference on Tools and algorithms for the construction and analysis of systems: part of the joint European conferences on theory and practice of software
Program sketching via CTL* model checking
Proceedings of the 18th international SPIN conference on Model checking software
Antichains and compositional algorithms for LTL synthesis
Formal Methods in System Design
CAV'10 Proceedings of the 22nd international conference on Computer Aided Verification
RATSY – a new requirements analysis tool with synthesis
CAV'10 Proceedings of the 22nd international conference on Computer Aided Verification
Synthesis of Reactive(1) designs
Journal of Computer and System Sciences
Recent challenges and ideas in temporal synthesis
SOFSEM'12 Proceedings of the 38th international conference on Current Trends in Theory and Practice of Computer Science
VMCAI'12 Proceedings of the 13th international conference on Verification, Model Checking, and Abstract Interpretation
Formal Methods in System Design
TACAS'12 Proceedings of the 18th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Template-Based controller synthesis for timed systems
TACAS'12 Proceedings of the 18th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Acacia+, a tool for LTL synthesis
CAV'12 Proceedings of the 24th international conference on Computer Aided Verification
Translating to Co-Büchi Made Tight, Unified, and Useful
ACM Transactions on Computational Logic (TOCL)
Tight bounds for the determinisation and complementation of generalised Büchi automata
ATVA'12 Proceedings of the 10th international conference on Automated Technology for Verification and Analysis
ATVA'12 Proceedings of the 10th international conference on Automated Technology for Verification and Analysis
The complexity of bounded synthesis for timed control with partial observability
FORMATS'12 Proceedings of the 10th international conference on Formal Modeling and Analysis of Timed Systems
Generalized reactivity(1) synthesis without a monolithic strategy
HVC'11 Proceedings of the 7th international Haifa Verification conference on Hardware and Software: verification and testing
Synthesizing nonanomalous event-based controllers for liveness goals
ACM Transactions on Software Engineering and Methodology (TOSEM)
Synthesis from LTL specifications with mean-payoff objectives
TACAS'13 Proceedings of the 19th international conference on Tools and Algorithms for the Construction and Analysis of Systems
SAT: Based bounded strong satisfiability checking of reactive system specifications
ICT-EurAsia'13 Proceedings of the 2013 international conference on Information and Communication Technology
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The bounded synthesis problem is to construct an implementation that satisfies a given temporal specification and a given bound on the number of states. We present a solution to the bounded synthesis problem for linear-time temporal logic (LTL), based on a novel emptiness-preserving translation from LTL to safety tree automata. For distributed architectures, where standard unbounded synthesis is in general undecidable, we show that bounded synthesis can be reduced to a SAT problem. As a result, we obtain an effective algorithm for the bounded synthesis from LTL specifications in arbitrary architectures. By iteratively increasing the bound, our construction can also be used as a semi-decision procedure for the unbounded synthesis problem.