On the synthesis of a reactive module
POPL '89 Proceedings of the 16th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Trace theory for automatic hierarchical verification of speed-independent circuits
Trace theory for automatic hierarchical verification of speed-independent circuits
On the development of reactive systems
Logics and models of concurrent systems
Reasoning about infinite computations
Information and Computation
Checking that finite state concurrent programs satisfy their linear specification
POPL '85 Proceedings of the 12th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Model checking
Synthesis of Communicating Processes from Temporal Logic Specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
Automata on Infinite Objects and Church's Problem
Automata on Infinite Objects and Church's Problem
Realizable and Unrealizable Specifications of Reactive Systems
ICALP '89 Proceedings of the 16th International Colloquium on Automata, Languages and Programming
On the Synthesis of an Asynchronous Reactive Module
ICALP '89 Proceedings of the 16th International Colloquium on Automata, Languages and Programming
The ForSpec Temporal Logic: A New Temporal Property-Specification Language
TACAS '02 Proceedings of the 8th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Small Progress Measures for Solving Parity Games
STACS '00 Proceedings of the 17th Annual Symposium on Theoretical Aspects of Computer Science
Language containment of non-deterministic omega-automata
CHARME '95 Proceedings of the IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Construction of Abstract State Graphs with PVS
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
MONA 1.x: New Techniques for WS1S and WS2S
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Synthesizing Processes and Schedulers from Temporal Specifications
CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification
An Automata-Theoretic Approach to Fair Realizability and Synthesis
Proceedings of the 7th International Conference on Computer Aided Verification
Mona & Fido: The Logic-Automaton Connection in Practice
CSL '97 Selected Papers from the11th International Workshop on Computer Science Logic
Deterministic generators and games for Ltl fragments
ACM Transactions on Computational Logic (TOCL)
FOCS '05 Proceedings of the 46th Annual IEEE Symposium on Foundations of Computer Science
From Nondeterministic Buchi and Streett Automata to Deterministic Parity Automata
LICS '06 Proceedings of the 21st Annual IEEE Symposium on Logic in Computer Science
A Practical Introduction to PSL (Series on Integrated Circuits and Systems)
A Practical Introduction to PSL (Series on Integrated Circuits and Systems)
Algorithmic Game Theory
On the complexity of omega -automata
SFCS '88 Proceedings of the 29th Annual Symposium on Foundations of Computer Science
Environment Assumptions for Synthesis
CONCUR '08 Proceedings of the 19th international conference on Concurrency Theory
CSL '08 Proceedings of the 22nd international workshop on Computer Science Logic
Genetic Programming and Model Checking: Synthesizing New Mutual Exclusion Algorithms
ATVA '08 Proceedings of the 6th International Symposium on Automated Technology for Verification and Analysis
Synthesis from Component Libraries
FOSSACS '09 Proceedings of the 12th International Conference on Foundations of Software Science and Computational Structures: Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2009
Better Quality in Synthesis through Quantitative Objectives
CAV '09 Proceedings of the 21st International Conference on Computer Aided Verification
An Antichain Algorithm for LTL Realizability
CAV '09 Proceedings of the 21st International Conference on Computer Aided Verification
Finite automata and their decision problems
IBM Journal of Research and Development
From Boolean to quantitative notions of correctness
Proceedings of the 37th annual ACM SIGPLAN-SIGACT symposium on Principles of programming languages
ATVA'07 Proceedings of the 5th international conference on Automated technology for verification and analysis
Model checking-based genetic programming with an application to mutual exclusion
TACAS'08/ETAPS'08 Proceedings of the Theory and practice of software, 14th international conference on Tools and algorithms for the construction and analysis of systems
Safraless procedures for timed specifications
FORMATS'10 Proceedings of the 8th international conference on Formal modeling and analysis of timed systems
Synthesis of trigger properties
LPAR'10 Proceedings of the 16th international conference on Logic for programming, artificial intelligence, and reasoning
Safraless compositional synthesis
CAV'06 Proceedings of the 18th international conference on Computer Aided Verification
CAV'10 Proceedings of the 22nd international conference on Computer Aided Verification
Synthesis of reactive(1) designs
VMCAI'06 Proceedings of the 7th international conference on Verification, Model Checking, and Abstract Interpretation
Verifying quantitative properties using bound functions
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
TACAS'10 Proceedings of the 16th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Observations on determinization of büchi automata
CIAA'05 Proceedings of the 10th international conference on Implementation and Application of Automata
Deterministic automata for the (f, g)-fragment of LTL
CAV'12 Proceedings of the 24th international conference on Computer Aided Verification
Automata with generalized rabin pairs for probabilistic model checking and LTL synthesis
CAV'13 Proceedings of the 25th international conference on Computer Aided Verification
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In automated synthesis, we transform a specification into a system that is guaranteed to satisfy the specification against all environments. While model-checking theory has led to industrial development and use of formal-verification tools, the integration of synthesis in the industry is slow. This has to do with theoretical limitations, like the complexity of the problem, algorithmic limitations, like the need to determinize automata on infinite words and solve parity games, methodological reasons, like the lack of satisfactory compositional synthesis algorithms, and practical reasons: current algorithms produce systems that satisfy the specification, but may do so in a peculiar way and may be larger or less well-structured than systems constructed manually. The research community has managed to suggest some solutions to these limitations, and bring synthesis algorithms closer to practice. Significant barriers, however, remain. Moreover, the integration of synthesis in real applications has taught us that the traditional setting of synthesis is too simplified and has brought with it new algorithmic challenges. This paper introduces the synthesis problem, algorithms for solving it, and recent promising ideas in making temporal-synthesis useful in practice.