Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Symbolic model checking: 1020 states and beyond
Information and Computation - Special issue: Selections from 1990 IEEE symposium on logic in computer science
Model checking and boolean graphs
Theoretical Computer Science - Selected papers of the 17th Colloquium on Trees in Algebra and Programming (CAAP '92) and of the European Symposium on Programming (ESOP), Rennes, France, Feb. 1992
Reasoning about infinite computations
Information and Computation
On characterization of safety and liveness properties in temporal logic
Proceedings of the fourth annual ACM symposium on Principles of distributed computing
Symbolic Model Checking
On the Synthesis of an Asynchronous Reactive Module
ICALP '89 Proceedings of the 16th International Colloquium on Automata, Languages and Programming
Model Checking of Safety Properties
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
Building Circuits from Relations
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Fast LTL to Büchi Automata Translation
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Infinite Games and Verification (Extended Abstract of a Tutorial)
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
NuSMV 2: An OpenSource Tool for Symbolic Model Checking
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
A Linear-Time Model-Checking Algorithm for the Alternation-Free Modal Mu-Calculus
CAV '91 Proceedings of the 3rd International Workshop on Computer Aided Verification
Some Progress in the Symbolic Verification of Timed Automata
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Automata logics, and infinite games
FOCS '05 Proceedings of the 46th Annual IEEE Symposium on Foundations of Computer Science
Optimizations for LTL Synthesis
FMCAD '06 Proceedings of the Formal Methods in Computer Aided Design
Interactive presentation: Automatic hardware synthesis from specifications: a case study
Proceedings of the conference on Design, automation and test in Europe
Specify, Compile, Run: Hardware from PSL
Electronic Notes in Theoretical Computer Science (ENTCS)
SMT-based synthesis of distributed systems
Proceedings of the second workshop on Automated formal methods
The temporal logic of programs
SFCS '77 Proceedings of the 18th Annual Symposium on Foundations of Computer Science
An Antichain Algorithm for LTL Realizability
CAV '09 Proceedings of the 21st International Conference on Computer Aided Verification
ATVA'07 Proceedings of the 5th international conference on Automated technology for verification and analysis
Compositional algorithms for LTL synthesis
ATVA'10 Proceedings of the 8th international conference on Automated technology for verification and analysis
Revisiting synthesis of GR(1) specifications
HVC'10 Proceedings of the 6th international conference on Hardware and software: verification and testing
On locally checkable properties
LPAR'06 Proceedings of the 13th international conference on Logic for Programming, Artificial Intelligence, and Reasoning
Solving games without determinization
CSL'06 Proceedings of the 20th international conference on Computer Science Logic
Robustness in the presence of liveness
CAV'10 Proceedings of the 22nd international conference on Computer Aided Verification
Synthesis of reactive(1) designs
VMCAI'06 Proceedings of the 7th international conference on Verification, Model Checking, and Abstract Interpretation
Selective approaches for solving weak games
ATVA'06 Proceedings of the 4th international conference on Automated Technology for Verification and Analysis
Acacia+, a tool for LTL synthesis
CAV'12 Proceedings of the 24th international conference on Computer Aided Verification
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Synthesizing finite-state systems from full linear-time temporal logic (LTL) is an ambitious way to tackle the challenge of constructing correct-by-construction systems. One particularly promising approach in this context is bounded synthesis, originally proposed by Schewe and Finkbeiner, which in turn builds upon Safraless synthesis, as described by Kupferman and Vardi. Previous implementations of these approaches performed the computation either in an explicit way or used symbolic data structures other than binary decision diagrams (BDDs). In this paper, we reconsider BDDs as state space representation and use it as data structure for bounded synthesis. The key to this construction is the application of two novel optimisation techniques that decrease the number of state bits in such a representation significantly. The first technique uses signalling bits to connect sub-games representing the safety- and non-safety parts of the specification. The second technique is based on a closer analysis of the step of building a safety game from a universal automaton and uses a sufficient condition to remove some so-called counters from the state space of the game.We evaluate our approach on several benchmark suites and show that the new approach leads to a computation time improvement of several orders of magnitude.