Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic
Logic of Programs, Workshop
Synthesizing Distributed Systems
LICS '01 Proceedings of the 16th Annual IEEE Symposium on Logic in Computer Science
Synthesis of communicating processes from temporal logic specifications
Synthesis of communicating processes from temporal logic specifications
LICS '05 Proceedings of the 20th Annual IEEE Symposium on Logic in Computer Science
FOCS '05 Proceedings of the 46th Annual IEEE Symposium on Foundations of Computer Science
ATVA'07 Proceedings of the 5th international conference on Automated technology for verification and analysis
SYCRAFT: A Tool for Synthesizing Distributed Fault-Tolerant Programs
CONCUR '08 Proceedings of the 19th international conference on Concurrency Theory
Does it pay to extend the perimeter of a world model?
FM'11 Proceedings of the 17th international conference on Formal methods
Formal Methods in System Design
Template-Based controller synthesis for timed systems
TACAS'12 Proceedings of the 18th international conference on Tools and Algorithms for the Construction and Analysis of Systems
The complexity of bounded synthesis for timed control with partial observability
FORMATS'12 Proceedings of the 10th international conference on Formal Modeling and Analysis of Timed Systems
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We apply SMT solving to synthesize distributed systems from specifications in linear-time temporal logic (LTL). The LTL formula is translated into an equivalent universal co-Büchi tree automaton. The existence of a finite transition system in the language of the automaton is then specified as a quantified formula in the theory (N,