Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Parametric real-time reasoning
STOC '93 Proceedings of the twenty-fifth annual ACM symposium on Theory of computing
Theoretical Computer Science
Discrete-time control for rectangular hybrid automata
Theoretical Computer Science
Linear Parametric Model Checking of Timed Automata
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Timed Control Synthesis for External Specifications
STACS '02 Proceedings of the 19th Annual Symposium on Theoretical Aspects of Computer Science
Timing Assumptions and Verification of Finite-State Concurrent Systems
Proceedings of the International Workshop on Automatic Verification Methods for Finite State Systems
Efficient on-the-fly algorithms for the analysis of timed games
CONCUR 2005 - Concurrency Theory
SMT-based synthesis of distributed systems
Proceedings of the second workshop on Automated formal methods
Synthesis from Component Libraries
FOSSACS '09 Proceedings of the 12th International Conference on Foundations of Software Science and Computational Structures: Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2009
An Antichain Algorithm for LTL Realizability
CAV '09 Proceedings of the 21st International Conference on Computer Aided Verification
Component-Based Abstraction Refinement for Timed Controller Synthesis
RTSS '09 Proceedings of the 2009 30th IEEE Real-Time Systems Symposium
UPPAAL-Tiga: time for playing games!
CAV'07 Proceedings of the 19th international conference on Computer aided verification
Timed control with observation based and stuttering invariant strategies
ATVA'07 Proceedings of the 5th international conference on Automated technology for verification and analysis
ATVA'07 Proceedings of the 5th international conference on Automated technology for verification and analysis
Combining symbolic representations for solving timed games
FORMATS'10 Proceedings of the 8th international conference on Formal modeling and analysis of timed systems
Synthia: verification and synthesis for timed automata
CAV'11 Proceedings of the 23rd international conference on Computer aided verification
CAV'10 Proceedings of the 22nd international conference on Computer Aided Verification
Counterexample-Guided synthesis of observation predicates
FORMATS'12 Proceedings of the 10th international conference on Formal Modeling and Analysis of Timed Systems
The complexity of bounded synthesis for timed control with partial observability
FORMATS'12 Proceedings of the 10th international conference on Formal Modeling and Analysis of Timed Systems
Semi-automatic controller design of Java-like models
Proceedings of the 15th Workshop on Formal Techniques for Java-like Programs
| Hi-index | 0.00 |
We present an effective controller synthesis method for real-time systems modeled as timed automata with safety requirements. Under the realistic assumption of partial observability, the problem is undecidable in general, and prohibitively expensive (2ExpTime-complete) if a bound on the granularity of the controller is set in advance. We investigate the synthesis of controllers from templates, given as timed automata with parametric control structure. Template-based synthesis is significantly cheaper (PSpace-complete) than standard synthesis and produces much simpler controllers. We present an efficient symbolic synthesis algorithm based on automatic abstraction refinement and report on encouraging experimental results from an implementation in the timed verification and synthesis tool synthia.