Supervisory control of a class of discrete event processes
SIAM Journal on Control and Optimization
Model checker aided design of a controller for a wafer scanner
International Journal on Software Tools for Technology Transfer (STTT)
Generation of concurrency control code using discrete-event systems theory
Proceedings of the 16th ACM SIGSOFT International Symposium on Foundations of software engineering
PETRI NETS '09 Proceedings of the 30th International Conference on Applications and Theory of Petri Nets
UPPAAL-Tiga: time for playing games!
CAV'07 Proceedings of the 19th international conference on Computer aided verification
A practical use of model checking for synthesis: generating a dam controller for flood management
Software—Practice & Experience
Synthesis of first-order dynamic programming algorithms
Proceedings of the 2011 ACM international conference on Object oriented programming systems languages and applications
Analyzing the effects of formal methods on the development of industrial control software
ICSM '11 Proceedings of the 2011 27th IEEE International Conference on Software Maintenance
Modeling complex systems with VeriJ
VECoS'11 Proceedings of the Fifth international conference on Verification and Evaluation of Computer and Communication Systems
Template-Based controller synthesis for timed systems
TACAS'12 Proceedings of the 18th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Software Maintenance through Supervisory Control
SEW '11 Proceedings of the 2011 IEEE 34th Software Engineering Workshop
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Controller synthesis consists in automatically generating a controller to restrict a hardware or software system so that it respects given requirements, for instance safety properties. Existing synthesis tools for discrete event systems mainly solve the problem for systems described in low-level formalisms. Controller synthesis, however, is not used in most industrial engineering processes. Barriers to wider adoption are the complexity of formally expressing the system and its requirements, the state explosion induced by large systems, and the limited confidence in the result, due to the difficulty in understanding the generated code. We propose an iterative, incremental, and semi-automatic approach to controller design, supporting the engineering process and mitigating state space explosion during synthesis. To provide a high-level environment, our approach is implemented in VeriJ, a Java-like language, and illustrated on a significant example taken from automated transport systems.