Model checker aided design of a controller for a wafer scanner

Authors:
Martijn Hendriks;Barend van den Nieuwelaar;Frits Vaandrager
Affiliations:
Institute for Computing and Information Sciences, Radboud University Nijmegen, Nijmegen, The Netherlands;ASML, Veldhoven, The Netherlands;Institute for Computing and Information Sciences, Radboud University Nijmegen, Nijmegen, The Netherlands
Venue:
International Journal on Software Tools for Technology Transfer (STTT)
Year:
2006

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Abstract

For a case-study of a wafer scanner from the semiconductor industry it is shown how model checking techniques can be used to compute (1) a simple yet optimal deadlock avoidance policy, and (2) an infinite schedule that optimizes throughput. in the absence of errors. Deadlock avoidance is studied based on a simple finite state model using Smv, and for throughput analysis a more detailed timed automaton model has been constructed and analyzed using the Uppaal tool. The Smv and Uppaal models are formally related through the notion of a stuttering bisimulation. The results were obtained within 2 weeks, which confirms once more that model checking techniques may help to improve the design process of realistic, industrial systems. Methodologically, the case study is interesting since two models were used to obtain results that could not have been obtained using only a single model.