From Timed Automata to Logic - and Back
MFCS '95 Proceedings of the 20th International Symposium on Mathematical Foundations of Computer Science
CMC: A Tool for Compositional Model-Checking of Real-Time Systems
FORTE XI / PSTV XVIII '98 Proceedings of the FIP TC6 WG6.1 Joint International Conference on Formal Description Techniques for Distributed Systems and Communication Protocols (FORTE XI) and Protocol Specification, Testing and Verification (PSTV XVIII)
Automata For Modeling Real-Time Systems
ICALP '90 Proceedings of the 17th International Colloquium on Automata, Languages and Programming
Verification of Large State/Event Systems Using Compositionality and Dependency Analysis
TACAS '98 Proceedings of the 4th International Conference on Tools and Algorithms for Construction and Analysis of Systems
The Impressive Power of Stopwatches
CONCUR '00 Proceedings of the 11th International Conference on Concurrency Theory
Timing Assumptions and Verification of Finite-State Concurrent Systems
Proceedings of the International Workshop on Automatic Verification Methods for Finite State Systems
Minimum-Cost Reachability for Priced Timed Automata
HSCC '01 Proceedings of the 4th International Workshop on Hybrid Systems: Computation and Control
Optimal Paths in Weighted Timed Automata
HSCC '01 Proceedings of the 4th International Workshop on Hybrid Systems: Computation and Control
Efficient Timed Reachability Analysis Using Clock Difference Diagrams
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
Job-Shop Scheduling Using Timed Automata
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Analysis of Timed Systems Based on Time-Abstracting Bisimulation
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Verification of Hierarchical State/Event Systems Using Reusability and Compositionality
TACAS '99 Proceedings of the 5th International Conference on Tools and Algorithms for Construction and Analysis of Systems
Efficient verification of real-time systems: compact data structure and state-space reduction
RTSS '97 Proceedings of the 18th IEEE Real-Time Systems Symposium
Lower and upper bounds in zone-based abstractions of timed automata
International Journal on Software Tools for Technology Transfer (STTT)
Model checker aided design of a controller for a wafer scanner
International Journal on Software Tools for Technology Transfer (STTT)
Formal Modeling and Scheduling of Datapaths of Digital Document Printers
FORMATS '08 Proceedings of the 6th international conference on Formal Modeling and Analysis of Timed Systems
Static guard analysis in timed automata verification
TACAS'03 Proceedings of the 9th international conference on Tools and algorithms for the construction and analysis of systems
Semantics and verification of a language for modelling hardware architectures
Formal methods and hybrid real-time systems
Developing UPPAAL over 15 years
Software—Practice & Experience
Collision Detection Algorithm for Deformable Objects Using OpenGL
MICCAI '02 Proceedings of the 5th International Conference on Medical Image Computing and Computer-Assisted Intervention-Part II
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The model-checker UPPAAL [LPY97] is based on the theory of timed automata [AD90] and its modeling languague offers additional features such as networks of timed automata, clocks and stop-watches, synchronizing over synchronous and broadcast channels, discrete variables ranging over bounded integers or structured types (arrays and records) as well as user-defined types and functions. The first version of UPPAAL was released in 1995 and since then there has been a continuous and still on-going development of datastructures and algorithms for its verification engine with particular emphasis on efficientmethods for reachability and nested reachability problems [BDL+10]. Over the years, the tool has consistently gained in performance and has by now been applied to the verification of numerous industrial case-studies. More recently the branch CORA [ALTP01, BFH+01] has emerged supporting cost-minimal reachability for priced timed automata, thus allowing for the optimization of several planning and scheduling problems to be solving using reachability checking [IKY+08, HvdNV06, AM01]. In the following we give an overview of the development of the datastuctures and algorithms underlying the verification engines of UPPAAL and CORA as well as indicate on-going research directions.