Theoretical Computer Science
UPPAAL—a tool suite for automatic verification of real-time systems
Proceedings of the DIMACS/SYCON workshop on Hybrid systems III : verification and control: verification and control
The Verilog hardware description language (4th ed.)
The Verilog hardware description language (4th ed.)
Proof, language, and interaction
The Designer's Guide to VHDL
Introduction to High-Level Synthesis
IEEE Design & Test
An interactive codesign environment for domain-specific coprocessors
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A Component-Based Design Environment for ESL Design
IEEE Design & Test
Symbolic and compositional reachability for timed automata
RP'10 Proceedings of the 4th international conference on Reachability problems
Verification, performance analysis and controller synthesis for real-time systems
FSEN'09 Proceedings of the Third IPM international conference on Fundamentals of Software Engineering
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In this paper we consider a high-level hardware description language Gezel, from which hardware can be synthesized through a translation to VHDL. The language is equipped with a simulator and supports exploration of hardware designs. The language has no semantics and it is difficult to get a deep understanding of many of the constructions. We therefore give a semantic domain for Gezel. Aiming at automated verification we relate this domain to the timed-automata model and we have experimented with verification of Gezel-specifications using the Uppaal system. In particular, we have proven the correctness of a hardware specification of the Simplified DES algorithm. We have also used Uppaal for small experiments of verifying resource usage.