On the synthesis of a reactive module
POPL '89 Proceedings of the 16th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Automata on Infinite Objects and Church's Problem
Automata on Infinite Objects and Church's Problem
Sequential Circuit Design Using Synthesis and Optimization
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Efficient Büchi Automata from LTL Formulae
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Building Circuits from Relations
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Freedom, Weakness, and Determinism: From Linear-Time to Branching-Time
LICS '98 Proceedings of the 13th Annual IEEE Symposium on Logic in Computer Science
Formal analysis of hardware requirements
Proceedings of the 43rd annual Design Automation Conference
Optimizations for LTL Synthesis
FMCAD '06 Proceedings of the Formal Methods in Computer Aided Design
A Practical Introduction to PSL (Series on Integrated Circuits and Systems)
A Practical Introduction to PSL (Series on Integrated Circuits and Systems)
A new algorithm for strategy synthesis in LTL games
TACAS'05 Proceedings of the 11th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Synthesis of reactive(1) designs
VMCAI'06 Proceedings of the 7th international conference on Verification, Model Checking, and Abstract Interpretation
Specify, Compile, Run: Hardware from PSL
Electronic Notes in Theoretical Computer Science (ENTCS)
ICALP '08 Proceedings of the 35th international colloquium on Automata, Languages and Programming, Part II
Environment Assumptions for Synthesis
CONCUR '08 Proceedings of the 19th international conference on Concurrency Theory
Compositional Synthesis of Reactive Systems from Live Sequence Chart Specifications
TACAS '09 Proceedings of the 15th International Conference on Tools and Algorithms for the Construction and Analysis of Systems: Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2009,
Interpolating functions from large Boolean relations
Proceedings of the 2009 International Conference on Computer-Aided Design
Synthesis of programs from temporal property specifications
MEMOCODE'09 Proceedings of the 7th IEEE/ACM international conference on Formal Methods and Models for Codesign
Anzu: a tool for property synthesis
CAV'07 Proceedings of the 19th international conference on Computer aided verification
RAT: a tool for the formal analysis of requirements
CAV'07 Proceedings of the 19th international conference on Computer aided verification
Diagnostic information for realizability
VMCAI'08 Proceedings of the 9th international conference on Verification, model checking, and abstract interpretation
Synthesis of trigger properties
LPAR'10 Proceedings of the 16th international conference on Logic for programming, artificial intelligence, and reasoning
AspectLTL: an aspect language for LTL specifications
Proceedings of the tenth international conference on Aspect-oriented software development
Generalized rabin(1) synthesis with applications to robust system synthesis
NFM'11 Proceedings of the Third international conference on NASA Formal methods
Debugging unrealizable specifications with model-based diagnosis
HVC'10 Proceedings of the 6th international conference on Hardware and software: verification and testing
Revisiting synthesis of GR(1) specifications
HVC'10 Proceedings of the 6th international conference on Hardware and software: verification and testing
Resolution proofs and Skolem functions in QBF evaluation and applications
CAV'11 Proceedings of the 23rd international conference on Computer aided verification
Evaluating LTL satisfiability solvers
ATVA'11 Proceedings of the 9th international conference on Automated technology for verification and analysis
Journal of Computer and System Sciences
Robustness in the presence of liveness
CAV'10 Proceedings of the 22nd international conference on Computer Aided Verification
Synthesis of Reactive(1) designs
Journal of Computer and System Sciences
VMCAI'12 Proceedings of the 13th international conference on Verification, Model Checking, and Abstract Interpretation
Effective synthesis of asynchronous systems from GR(1) specifications
VMCAI'12 Proceedings of the 13th international conference on Verification, Model Checking, and Abstract Interpretation
Towards a notion of unsatisfiable and unrealizable cores for LTL
Science of Computer Programming
Formal Methods in System Design
TACAS'12 Proceedings of the 18th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Unified QBF certification and its applications
Formal Methods in System Design
CAV'12 Proceedings of the 24th international conference on Computer Aided Verification
Generalized reactivity(1) synthesis without a monolithic strategy
HVC'11 Proceedings of the 7th international Haifa Verification conference on Hardware and Software: verification and testing
Synthesizing nonanomalous event-based controllers for liveness goals
ACM Transactions on Software Engineering and Methodology (TOSEM)
Propositional temporal proving with reductions to a SAT problem
CADE'13 Proceedings of the 24th international conference on Automated Deduction
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We propose to use a formal specification language as a high-level hardware description language. Formal languages allow for compact, unambiguous representations and yield designs that are correct by construction. The idea of automatic synthesis from specifications is old, but used to be completely impractical. Recently, great strides towards efficient synthesis from specifications have been made. In this paper we extend these recent methods to generate compact circuits and we show their practicality by synthesizing an arbiter for ARM's AMBA AHB bus and a generalized-buffer from specifications given in PSL. These are the first industrial examples that have been synthesized automatically from their specifications.