On the synthesis of a reactive module
POPL '89 Proceedings of the 16th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Realizable and Unrealizable Specifications of Reactive Systems
ICALP '89 Proceedings of the 16th International Colloquium on Automata, Languages and Programming
Finding the Causes of Unrealizability of Reactive System Formal Specifications
SEFM '04 Proceedings of the Software Engineering and Formal Methods, Second International Conference
Error explanation and fault localization with distance metrics
Error explanation and fault localization with distance metrics
Formal analysis of hardware requirements
Proceedings of the 43rd annual Design Automation Conference
Synthesis of Open Reactive Systems from Scenario-Based Specifications
Fundamenta Informaticae - Application of Concurrency to System Design (ACSD'03)
Interactive presentation: Automatic hardware synthesis from specifications: a case study
Proceedings of the conference on Design, automation and test in Europe
On the complexity of omega -automata
SFCS '88 Proceedings of the 29th Annual Symposium on Foundations of Computer Science
UPPAAL-Tiga: time for playing games!
CAV'07 Proceedings of the 19th international conference on Computer aided verification
RAT: a tool for the formal analysis of requirements
CAV'07 Proceedings of the 19th international conference on Computer aided verification
Boolean abstraction for temporal logic satisfiability
CAV'07 Proceedings of the 19th international conference on Computer aided verification
Synthesis of reactive(1) designs
VMCAI'06 Proceedings of the 7th international conference on Verification, Model Checking, and Abstract Interpretation
AspectLTL: an aspect language for LTL specifications
Proceedings of the tenth international conference on Aspect-oriented software development
Debugging unrealizable specifications with model-based diagnosis
HVC'10 Proceedings of the 6th international conference on Hardware and software: verification and testing
Analyzing unsynthesizable specifications for high-level robot behavior using LTLMoP
CAV'11 Proceedings of the 23rd international conference on Computer aided verification
Towards a notion of unsatisfiable cores for LTL
FSEN'09 Proceedings of the Third IPM international conference on Fundamentals of Software Engineering
Synthesis of Reactive(1) designs
Journal of Computer and System Sciences
Two-way traceability and conflict debugging for AspectLTL programs
Proceedings of the 11th annual international conference on Aspect-oriented Software Development
Towards a notion of unsatisfiable and unrealizable cores for LTL
Science of Computer Programming
Least-violating control strategy synthesis with safety rules
Proceedings of the 16th international conference on Hybrid systems: computation and control
Counter play-out: executing unrealizable scenario-based specifications
Proceedings of the 2013 International Conference on Software Engineering
Two-Way traceability and conflict debugging for AspectLTL programs
Transactions on Aspect-Oriented Software Development X
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Realizability - checking whether a specification can be implemented by an open system - is a fundamental step in the design flow. However, if the specification turns out not to be realizable, there is no method to pinpoint the causes for unrealizability. In this paper, we address the open problem of providing diagnostic information for realizability: we formally define the notion of (minimal) explanation of (un)realizability, we propose algorithms to compute such explanations, and provide a preliminary experimental evaluation.