Computer-aided verification of coordinating processes: the automata-theoretic approach
Computer-aided verification of coordinating processes: the automata-theoretic approach
VIS: A System for Verification and Synthesis
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Formal analysis of hardware requirements
Proceedings of the 43rd annual Design Automation Conference
Interactive presentation: Automatic hardware synthesis from specifications: a case study
Proceedings of the conference on Design, automation and test in Europe
Synthesis of reactive(1) designs
VMCAI'06 Proceedings of the 7th international conference on Verification, Model Checking, and Abstract Interpretation
A Framework for Inherent Vacuity
HVC '08 Proceedings of the 4th International Haifa Verification Conference on Hardware and Software: Verification and Testing
Diagnostic information for realizability
VMCAI'08 Proceedings of the 9th international conference on Verification, model checking, and abstract interpretation
A model advisor for NuSMV specifications
Innovations in Systems and Software Engineering
Towards a notion of unsatisfiable cores for LTL
FSEN'09 Proceedings of the Third IPM international conference on Fundamentals of Software Engineering
RATSY – a new requirements analysis tool with synthesis
CAV'10 Proceedings of the 22nd international conference on Computer Aided Verification
Synthesis of Reactive(1) designs
Journal of Computer and System Sciences
Towards a notion of unsatisfiable and unrealizable cores for LTL
Science of Computer Programming
Synthesis from incompatible specifications
Proceedings of the tenth ACM international conference on Embedded software
Automatic generation of quality specifications
CAV'13 Proceedings of the 25th international conference on Computer Aided Verification
Behavioral diagnosis of LTL specifications at operator level
IJCAI'13 Proceedings of the Twenty-Third international joint conference on Artificial Intelligence
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Formal languages are increasingly used to describe the functional requirements of circuits. Although formal requirements can be hard to understand and subtle, they are seldom the object of verification. In this paper we present our requirement analysis tool, RAT. Our tool supports quality assurance of formal specifications. A designer can interactively explore the requirements' semantics and automatically check the specification against assertions (which must be satisfied) and possibilities (which describe allowed corner-case behavior). Using RAT, a designer can also investigate the realizability of a specification. RAT was successfully examined in several industrial projects.