Counterexample-Guided Abstraction Refinement
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Combinatorial sketching for finite programs
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
Interactive presentation: Automatic hardware synthesis from specifications: a case study
Proceedings of the conference on Design, automation and test in Europe
Specify, Compile, Run: Hardware from PSL
Electronic Notes in Theoretical Computer Science (ENTCS)
Sketching concurrent data structures
Proceedings of the 2008 ACM SIGPLAN conference on Programming language design and implementation
The temporal logic of programs
SFCS '77 Proceedings of the 18th Annual Symposium on Foundations of Computer Science
ATVA'07 Proceedings of the 5th international conference on Automated technology for verification and analysis
TACAS'08/ETAPS'08 Proceedings of the Theory and practice of software, 14th international conference on Tools and algorithms for the construction and analysis of systems
TACAS'12 Proceedings of the 18th international conference on Tools and Algorithms for the Construction and Analysis of Systems
TRANSIT: specifying protocols with concolic snippets
Proceedings of the 34th ACM SIGPLAN conference on Programming language design and implementation
PARTY: parameterized synthesis of token rings
CAV'13 Proceedings of the 25th international conference on Computer Aided Verification
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We present an automatic method for the synthesis of processes in a reactive system from specifications in linear-time temporal logic (LTL). The synthesis algorithm executes a loop consisting of three phases: Solve, Check, and Refine. In the Solve phase, a candidate solution is obtained as a model of a Boolean constraint system; in the Check phase, the candidate solution is checked for reachable error states; in the Refine phase, the constraint system is refined to eliminate any errors found in the Check phase. The algorithm terminates when an implementation without errors is found. We call our approach "lazy," because constraints on possible process implementations are only considered incrementally, as needed to rule out incorrect candidate solutions. This contrasts with the standard "eager" approach, where the full specification is considered right away. We report on experience in the arbiter synthesis for the AMBA bus protocol, where lazy synthesis leads to significantly smaller implementations than the previous eager approach.