Limits for automatic verification of finite-state concurrent systems
Information Processing Letters
Proving properties of a ring of finite-state machines
Information Processing Letters
On the synthesis of a reactive module
POPL '89 Proceedings of the 16th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Reasoning about systems with many processes
Journal of the ACM (JACM)
Verifying parameterized networks
ACM Transactions on Programming Languages and Systems (TOPLAS)
Reducing Model Checking of the Many to the Few
CADE-17 Proceedings of the 17th International Conference on Automated Deduction
LICS '05 Proceedings of the 20th Annual IEEE Symposium on Logic in Computer Science
FOCS '05 Proceedings of the 46th Annual IEEE Symposium on Foundations of Computer Science
Interactive presentation: Automatic hardware synthesis from specifications: a case study
Proceedings of the conference on Design, automation and test in Europe
Specify, Compile, Run: Hardware from PSL
Electronic Notes in Theoretical Computer Science (ENTCS)
Distributed reactive systems are hard to synthesize
SFCS '90 Proceedings of the 31st Annual Symposium on Foundations of Computer Science
Proceedings of the the 7th joint meeting of the European software engineering conference and the ACM SIGSOFT symposium on The foundations of software engineering
Synthesis of asynchronous systems
LOPSTR'06 Proceedings of the 16th international conference on Logic-based program synthesis and transformation
ATVA'07 Proceedings of the 5th international conference on Automated technology for verification and analysis
TACAS'08/ETAPS'08 Proceedings of the Theory and practice of software, 14th international conference on Tools and algorithms for the construction and analysis of systems
Synthesizing solutions to the leader election problem using model checking and genetic programming
HVC'09 Proceedings of the 5th international Haifa verification conference on Hardware and software: verification and testing
Dynamic cutoff detection in parameterized concurrent programs
CAV'10 Proceedings of the 22nd international conference on Computer Aided Verification
Synthesis of reactive(1) designs
VMCAI'06 Proceedings of the 7th international conference on Verification, Model Checking, and Abstract Interpretation
Reasoning about threads communicating via locks
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
VMCAI'12 Proceedings of the 13th international conference on Verification, Model Checking, and Abstract Interpretation
Model checking and abstraction to the aid of parameterized systems (a survey)
Computer Languages, Systems and Structures
PARTY: parameterized synthesis of token rings
CAV'13 Proceedings of the 25th international conference on Computer Aided Verification
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We study the synthesis problem for distributed architectures with a parametric number of finite-state components. Parameterized specifications arise naturally in a synthesis setting, but thus far it was unclear how to decide realizability and how to perform synthesis. Using a classical result from verification, we show that for specifications in LTL\X, parameterized synthesis of token ring networks is equivalent to distributed synthesis of a network consisting of a few copies of a single process. Adapting a result from distributed synthesis, we show that the latter problem is undecidable. We then describe a semi-decision procedure based on bounded synthesis and show applicability on a simple case study. Finally, we sketch a general framework for parameterized synthesis based on cut-off results for verification.