On the synthesis of a reactive module
POPL '89 Proceedings of the 16th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
IEEE Transactions on Software Engineering - Special issue on formal methods in software practice
An automata-theoretic approach to branching-time model checking
Journal of the ACM (JACM)
NuSMV 2: An OpenSource Tool for Symbolic Model Checking
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Freedom, Weakness, and Determinism: From Linear-Time to Branching-Time
LICS '98 Proceedings of the 13th Annual IEEE Symposium on Logic in Computer Science
FOCS '05 Proceedings of the 46th Annual IEEE Symposium on Foundations of Computer Science
Combinatorial sketching for finite programs
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
On the complexity of omega -automata
SFCS '88 Proceedings of the 29th Annual Symposium on Foundations of Computer Science
An Antichain Algorithm for LTL Realizability
CAV '09 Proceedings of the 21st International Conference on Computer Aided Verification
ATVA'07 Proceedings of the 5th international conference on Automated technology for verification and analysis
Unbeast: symbolic bounded synthesis
TACAS'11/ETAPS'11 Proceedings of the 17th international conference on Tools and algorithms for the construction and analysis of systems: part of the joint European conferences on theory and practice of software
Synthesis of loop-free programs
Proceedings of the 32nd ACM SIGPLAN conference on Programming language design and implementation
Synthesis of reactive(1) designs
VMCAI'06 Proceedings of the 7th international conference on Verification, Model Checking, and Abstract Interpretation
Strategy composition in compositional games
ICALP'13 Proceedings of the 40th international conference on Automata, Languages, and Programming - Volume Part II
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Synthesis of correct by design systems from specification has recently attracted much attention. The theoretical results imply that this problem is highly intractable, e.g., synthesizing a system is 2EXPTIME-complete for an LTL specification and EXPTIME-complete for CTL. An argument in favor of synthesis is that the temporal specification is highly compact, and the complexity reflects the large size of the system constructed. A careful observation reveals that the size of the system is presented in such arguments as the size of its state space. This view is a bit biased, in the sense that the state space can be exponentially larger than the size of a reasonable implementation such as a circuit or a program. Although this alternative measure of the size of the synthesized system is more intuitive (e.g., this is the standard way model checking problems are measured), research on synthesis has so far stayed with measuring the system in terms of the explicit state space. This raises the question of whether or not there exists a small bound on the circuits or programs. In this paper, we show that this is the case if, and only if, PSPACE = EXPTIME.