On the synthesis of a reactive module
POPL '89 Proceedings of the 16th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Optimizations for LTL Synthesis
FMCAD '06 Proceedings of the Formal Methods in Computer Aided Design
Sketching concurrent data structures
Proceedings of the 2008 ACM SIGPLAN conference on Programming language design and implementation
Efficient E-Matching for SMT Solvers
CADE-21 Proceedings of the 21st international conference on Automated Deduction: Automated Deduction
CAV '08 Proceedings of the 20th international conference on Computer Aided Verification
A solver for QBFs in negation normal form
Constraints
Constraint-Based Invariant Inference over Predicate Abstraction
VMCAI '09 Proceedings of the 10th International Conference on Verification, Model Checking, and Abstract Interpretation
Boolector: An Efficient SMT Solver for Bit-Vectors and Arrays
TACAS '09 Proceedings of the 15th International Conference on Tools and Algorithms for the Construction and Analysis of Systems: Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2009,
Handbook of Practical Logic and Automated Reasoning
Handbook of Practical Logic and Automated Reasoning
Program verification using templates over predicate abstraction
Proceedings of the 2009 ACM SIGPLAN conference on Programming language design and implementation
Complete Instantiation for Quantified Formulas in Satisfiabiliby Modulo Theories
CAV '09 Proceedings of the 21st International Conference on Computer Aided Verification
Beyond CNF: A Circuit-Based QBF Solver
SAT '09 Proceedings of the 12th International Conference on Theory and Applications of Satisfiability Testing
From program verification to program synthesis
Proceedings of the 37th annual ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Fault localization and correction with QBF
SAT'07 Proceedings of the 10th international conference on Theory and applications of satisfiability testing
CAV'07 Proceedings of the 19th international conference on Computer aided verification
BAT: the bit-level analysis tool
CAV'07 Proceedings of the 19th international conference on Computer aided verification
A decision procedure for bit-vectors and arrays
CAV'07 Proceedings of the 19th international conference on Computer aided verification
TACAS'08/ETAPS'08 Proceedings of the Theory and practice of software, 14th international conference on Tools and algorithms for the construction and analysis of systems
Oracle-guided component-based program synthesis
Proceedings of the 32nd ACM/IEEE International Conference on Software Engineering - Volume 1
SAT'04 Proceedings of the 7th international conference on Theory and Applications of Satisfiability Testing
Schema-guided synthesis of imperative programs by constraint solving
LOPSTR'04 Proceedings of the 14th international conference on Logic Based Program Synthesis and Transformation
Integrating dependency schemes in search-based QBF solvers
SAT'10 Proceedings of the 13th international conference on Theory and Applications of Satisfiability Testing
Ranking function synthesis for bit-vector relations
TACAS'10 Proceedings of the 16th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Word-Level Predicate-Abstraction and Refinement Techniques for Verifying RTL Verilog
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Data-driven equivalence checking
Proceedings of the 2013 ACM SIGPLAN international conference on Object oriented programming systems languages & applications
Solving existentially quantified horn clauses
CAV'13 Proceedings of the 25th international conference on Computer Aided Verification
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In recent years, bit-precise reasoning has gained importance in hardware and software verification. Of renewed interest is the use of symbolic reasoning for synthesising loop invariants, ranking functions, or whole program fragments and hardware circuits. Solvers for the quantifier-free fragment of bit-vector logic exist and often rely on SAT solvers for efficiency. However, many techniques require quantifiers in bit-vector formulas to avoid an exponential blow-up during construction. Solvers for quantified formulas usually flatten the input to obtain a quantified Boolean formula, losing much of the word-level information in the formula. We present a new approach based on a set of effective word-level simplifications that are traditionally employed in automated theorem proving, heuristic quantifier instantiation methods used in SMT solvers, and model finding techniques based on skeletons/templates. Experimental results on two different types of benchmarks indicate that our method outperforms the traditional flattening approach by multiple orders of magnitude of runtime.