Path predicate abstraction by complete interval property checking
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
Efficiently solving quantified bit-vector formulas
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
Formal hardware/software co-verification by interval property checking with abstraction
Proceedings of the 48th Design Automation Conference
An automata-theoretic approach to hardware/software co-verification
FASE'10 Proceedings of the 13th international conference on Fundamental Approaches to Software Engineering
Efficiently solving quantified bit-vector formulas
Formal Methods in System Design
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As a first step, most model checkers used in the hardware industry convert a high-level register-transfer-level (RTL) design into a netlist. However, algorithms that operate at the netlist level are unable to exploit the structure of the higher abstraction levels and, thus, are less scalable. The RTL of a hardware description language such as Verilog is similar to a software program with special features for hardware design such as bit-vector arithmetic and concurrency. This paper uses predicate abstraction, a software verification technique, for verifying RTL Verilog. There are two challenges when applying predicate abstraction to circuits: 1) the computation of the abstract model in presence of a large number of predicates and 2) the discovery of suitable word-level predicates for abstraction refinement. We address the first problem using a technique called predicate clustering. We address the second problem by computing the weakest preconditions of Verilog statements in order to obtain new word-level predicates during abstraction refinement. We compare the performance of our technique with localization reduction, a netlist-level abstraction technique, and report improvements on a set of benchmarks.