Computer-aided verification of coordinating processes: the automata-theoretic approach
Computer-aided verification of coordinating processes: the automata-theoretic approach
Symbolic model checking using SAT procedures instead of BDDs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Automatic predicate abstraction of C programs
Proceedings of the ACM SIGPLAN 2001 conference on Programming language design and implementation
Generic control flow reconstruction from assembly code
Proceedings of the joint conference on Languages, compilers and tools for embedded systems: software and compilers for embedded systems
Progress on the State Explosion Problem in Model Checking
Informatics - 10 Years Back. 10 Years Ahead.
Counterexample-guided abstraction refinement for symbolic model checking
Journal of the ACM (JACM)
Iterative Abstraction using SAT-based BMC with Proof Analysis
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Transition predicate abstraction and fair termination
Proceedings of the 32nd ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Transition predicate abstraction and fair termination
Proceedings of the 32nd ACM SIGPLAN-SIGACT symposium on Principles of programming languages
HW/SW co-verification of embedded systems using bounded model checking
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Using CTL formulae as component abstraction in a design and verification flow
ACSD '07 Proceedings of the Seventh International Conference on Application of Concurrency to System Design
ICESS '09 Proceedings of the 2009 International Conference on Embedded Software and Systems
Path predicate abstraction by complete interval property checking
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
Word-Level Predicate-Abstraction and Refinement Techniques for Verifying RTL Verilog
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Unbounded Protocol Compliance Verification Using Interval Property Checking With Invariants
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Ensuring functional correctness of hardware and software is a bottleneck in every design process of Embedded Systems. This paper proposes an approach to formally verify low-level software in conjunction with the hardware. The proposed approach is based on Interval Property Checking (IPC) that has proved successful on large industrial hardware designs. In this paper, IPC is extended by a specific abstraction technique that makes it tractable for hardware/software co-verification on realistic industrial designs. In the proposed methodology sets of finite state sequences of the system are abstracted by interval properties. This allows us to handle long sequences of state transitions in the hardware as they occur when running programs. We demonstrate the feasibility of our approach using the example of an industrial LIN software running on a public domain microprocessor platform.