Contradictory antecedent debugging in bounded model checking
Proceedings of the 19th ACM Great Lakes symposium on VLSI
WoLFram- A Word Level Framework for Formal Verification
RSP '09 Proceedings of the 2009 IEEE/IFIP International Symposium on Rapid System Prototyping
Generating an Efficient Instruction Set Simulator from a Complete Property Suite
RSP '09 Proceedings of the 2009 IEEE/IFIP International Symposium on Rapid System Prototyping
Analyzing k-step induction to compute invariants for SAT-based property checking
Proceedings of the 47th Design Automation Conference
Property analysis and design understanding
Proceedings of the Conference on Design, Automation and Test in Europe
Automated formal verification of processors based on architectural models
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
Path predicate abstraction by complete interval property checking
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
Formal hardware/software co-verification by interval property checking with abstraction
Proceedings of the 48th Design Automation Conference
Property-specific sequential invariant extraction for SAT-based unbounded model checking
Proceedings of the International Conference on Computer-Aided Design
Using sequence diagrams to specify and to generate RTL assertions
VECoS'11 Proceedings of the Fifth international conference on Verification and Evaluation of Computer and Communication Systems
System verification of concurrent RTL modules by compositional path predicate abstraction
Proceedings of the 49th Annual Design Automation Conference
A guiding coverage metric for formal verification
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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We propose a methodology to formally prove protocol compliance for communication blocks in System-on-Chip (SoC) designs. In this methodology, a set of operational properties is specified with respect to the states of a central finite state machine (FSM). This central FSM is called main FSM and controls the overall behavior of the design. In order to prove a set of compliance properties, we developed an approach that combines property checking on a bounded circuit model with an approximate reachability analysis. The property checker determines whether a property is valid for an arbitrary state of the design regardless of its reachability. In order to avoid false negatives, reachability constraints are added to the property, which are generated by an approximate FSM traversal algorithm. We show how the existence of a main FSM can be exploited systematically in the reachability analysis and how to partition both the transition relation and the state space such that the computational complexity is reduced drastically. This makes formal verification of protocol compliance tractable even for large designs with several thousand state variables. Our approach has been applied successfully to verify several industrial designs.