Formally verifying a microprocessor using a simulation methodology
DAC '94 Proceedings of the 31st annual Design Automation Conference
Model checking
Efficient Detection of Vacuity in Temporal Model Checking
Formal Methods in System Design - Special issue on CAV '97
Checking Safety Properties Using Induction and a SAT-Solver
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Applying SAT Methods in Unbounded Symbolic Model Checking
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Efficient Detection of Vacuity in ACTL Formulas
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Cost-Efficient Block Verification for a UMTS Up-Link Chip-Rate Coprocessor
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Computer Organization and Design
Computer Organization and Design
AMUSE: a minimally-unsatisfiable subformula extractor
Proceedings of the 41st annual Design Automation Conference
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Verification of Proofs of Unsatisfiability for CNF Formulas
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
MUP: a minimal unsatisfiability prover
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Exploiting Resolution Proofs to Speed Up LTL Vacuity Detection for BMC
FMCAD '07 Proceedings of the Formal Methods in Computer Aided Design
Easier and More Informative Vacuity Checks
MEMOCODE '07 Proceedings of the 5th IEEE/ACM International Conference on Formal Methods and Models for Codesign
On finding all minimally unsatisfiable subformulas
SAT'05 Proceedings of the 8th international conference on Theory and Applications of Satisfiability Testing
A branch-and-bound algorithm for extracting smallest minimal unsatisfiable formulas
SAT'05 Proceedings of the 8th international conference on Theory and Applications of Satisfiability Testing
Unbounded Protocol Compliance Verification Using Interval Property Checking With Invariants
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Temporal antecedent failure: refining vacuity
CONCUR'07 Proceedings of the 18th international conference on Concurrency Theory
WoLFram- A Word Level Framework for Formal Verification
RSP '09 Proceedings of the 2009 IEEE/IFIP International Symposium on Rapid System Prototyping
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In the context of formal verification Bounded Model Checking (BMC) has shown to be very powerful for large industrial designs. BMC is used to check whether a circuit satisfies a temporal property or not. Typically, such a property is formulated as an implication. In the antecedent of the property the verification engineer specifies the assumptions about the design environment and joins the respective expressions by logical AND. However, the overall conjunction may have no solution, i.e. the antecedent is contradictory. Since in this case a property trivially holds this situation has to be avoided. Furthermore, the root cause of a contradictory antecedent has to be identified which is a manual and very time-consuming process. In this paper we propose a fully automatic approach for presenting all reasons of a contradictory antecedent to the verification engineer, i.e. the approach pinpoints to the sub-expressions in the antecedent that form a contradiction. Hence, our approach reduces the debugging time of a contradictory antecedent significantly.