Facile: a language and compiler for high-performance processor simulators
Proceedings of the ACM SIGPLAN 2001 conference on Programming language design and implementation
The DLX Instruction Set Architecture Handbook
The DLX Instruction Set Architecture Handbook
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Integrated Verification Approach during ADL-Driven Processor Design
RSP '06 Proceedings of the Seventeenth IEEE International Workshop on Rapid System Prototyping
A universal technique for fast and flexible instruction-set architecture simulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Unbounded Protocol Compliance Verification Using Interval Property Checking With Invariants
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Automated formal verification of processors based on architectural models
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
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Instruction set simulators can be used for the early development andtesting of software for a processor before it is manufactured. Whilegate-level simulation of the overall design offers cycle-accurateresults, performance of the simulation is typically not sufficient forin-depth software testing. In addition, such a gate-level simulationcannot be carried out in the early phases of the design process whenonly the instruction set architecture (ISA) is present and the designis not yet complete. Therefore, more abstract simulators are based onthe ISA; these simulators can achieve a performance of several millioninstructions per second. However, by introducing a simulator separatefrom the design, the ISA has to be re-implemented for thesimulator. Therefore, there is a risk that the instruction setsimulator is not in sync with the design or the ISA. We present anapproach to automatically generate an instruction set simulator from acomplete property suite, which can be used for the formal verificationof the processor. In this way, we obtain a provably correct simulatorwith relatively small effort. We show the feasibility of the approachfor an industrial design; the performance of the resulting simulatoris comparable to custom state-of-the-art simulators.