Fast cycle-accurate simulation and instruction set generation for constraint-based descriptions of programmable architectures

  • Authors:

  • Scott J. Weber;Matthew W. Moskewicz;Matthias Gries;Christian Sauer;Kurt Keutzer

  • Affiliations:

  • University of California, Berkeley, CA;University of California, Berkeley, CA;University of California, Berkeley, CA;Infineon Technologies, Munich, Germany;University of California, Berkeley, CA

  • Venue:
  • Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
  • Year:
  • 2004

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Abstract

State-of-the-art architecture description languages have been successfully used to model application-specific programmable architectures limited to particular control schemes. In this paper, we introduce a language and methodology that provide a framework for constructing and simulating a wider range of architectures. The framework exploits the fact that designers are often only concerned with data paths, not the instruction set and control. In the framework, each processing element is described in a structural language that only requires the specification of the data path and constraints on how it can be used. From such a description, the supported operations of the processing element are automatically extracted and a controller is generated. Various architectures are then realized by composing the processing elements. Furthermore, hardware descriptions and bit-true cycle-accurate simulators are automatically generated. Results show that our simulators are up to an order of magnitude faster than other reported simulators of this type and two orders of magnitude faster than equivalent Verilog simulations.