DAC '96 Proceedings of the 33rd annual Design Automation Conference
Insulin: An Instruction Set Simulation Environment
CHDL '93 Proceedings of the 11th IFIP WG10.2 International Conference sponsored by IFIP WG10.2 and in cooperation with IEEE COMPSOC on Computer Hardware Description Languages and their Applications
Describing instruction set processors using nML
EDTC '95 Proceedings of the 1995 European conference on Design and Test
A processor desription language supporting retargetable multi-pipeline DSP program development tools
Proceedings of the 11th international symposium on System synthesis
HDL-based modeling of embedded processor behavior for retargetable compilation
Proceedings of the 11th international symposium on System synthesis
A methodology for accurate performance evaluation in architecture exploration
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
LISA—machine description language for cycle-accurate models of programmable DSP architectures
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Retargetable compiled simulation of embedded processors using a machine description language
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Generating production quality software development tools using a machine description language
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 14th international symposium on Systems synthesis
A universal technique for fast and flexible instruction-set architecture simulation
Proceedings of the 39th annual Design Automation Conference
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
An ultra-fast instruction set simulator
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A retargetable micro-architecture simulator
Proceedings of the 40th annual Design Automation Conference
Instruction set compiled simulation: a technique for fast and flexible instruction set simulation
Proceedings of the 40th annual Design Automation Conference
Architecture Implementation Using the Machine Description Language LISA
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
An efficient retargetable framework for instruction-set simulation
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Techniques for accurate performance evaluation in architecture exploration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ICDCSW '04 Proceedings of the 24th International Conference on Distributed Computing Systems Workshops - W7: EC (ICDCSW'04) - Volume 7
A novel approach for flexible and consistent ADL-driven ASIP design
Proceedings of the 41st annual Design Automation Conference
Fast Cycle-accurate Behavioral Simulation for Pipelined Processors Using Early Pipeline Evaluation
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
DynamoSim: a trace-based dynamically compiled instruction set simulator
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
The ArchC architecture description language and tools
International Journal of Parallel Programming
A retargetable framework for instruction-set architecture simulation
ACM Transactions on Embedded Computing Systems (TECS)
An open-source binary utility generator
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 2007 Summer Computer Simulation Conference
Processor Description Languages
Processor Description Languages
Hybrid-compiled simulation: An efficient technique for instruction-set architecture simulation
ACM Transactions on Embedded Computing Systems (TECS)
Model checking of software for microcontrollers
ACM Transactions on Embedded Computing Systems (TECS)
A model-driven automatically-retargetable debug tool for embedded systems
SAMOS'07 Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation
A flexible approach to automated development of cross toolkits for embedded systems
PSI'09 Proceedings of the 7th international Andrei Ershov Memorial conference on Perspectives of Systems Informatics
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An experimental set of tools that generate instruction set simulators,assemblers, and disassemblers from a single description wasdeveloped to test if retargetable development tools would work forcommercial DSP processors and microprocessors. The processorinstruction set was described using a language called nML. TheTMS320C50 DSP processor and the ARM7 microprocessor weremodeled in nML. The resulting instruction set models executeabout 25,000 instructions per second, and compiled instruction setsimulation models execute about 150,000 instructions per second.The viability of this approach and the deficiencies of nML are discussed.