Techniques for accurate performance evaluation in architecture exploration

  • Authors:

  • George Hadjiyiannis;Srinivas Devadas

  • Affiliations:

  • Tenara Limited, Cambridge, MA;Laboratory for Computer Science, Massachusetts Institute of Technology, Cambridge, MA

  • Venue:
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • Year:
  • 2003

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Abstract

We present a system that automatically generates a cycle-accurate and bit-true instruction level simulator (ILS) and a hardware implementation model given a description of a target processor. An ILS can be used to obtain a cycle count for a given program running on the target architecture, while the cycle length, die size, and power consumption can be obtained from the hard-ware implementation model. These figures allow us to accurately and rapidly evaluate target architectures within an architecture exploration methodology for system-level synthesis.In an architecture exploration scheme, both the ILS and the hardware model must be generated automatically, else a substantial programming and hardware design effort has to be expended in each design iteration. Our system uses the Instruction Set Description language to support the automatic generation of the ILS and the hardware synthesis model, as wall as other related tools.