Retargetable Compiler Code Generation
ACM Computing Surveys (CSUR)
The Art of Computer Programming, 2nd Ed. (Addison-Wesley Series in Computer Science and Information
The Art of Computer Programming, 2nd Ed. (Addison-Wesley Series in Computer Science and Information
Structure of Computers and Computations
Structure of Computers and Computations
The Design of a Subprocessor with Dynamic Microprogramming with MIMOLA
GI-NTG Fachtagung Struktur und Betrieb von Rechensystemen
A method of automatic data path synthesis
DAC '83 Proceedings of the 20th Design Automation Conference
The MIMOLA design system a computer aided digital processor design method
DAC '79 Proceedings of the 16th Design Automation Conference
The MIMOLA design system: Detailed description of the software system
DAC '79 Proceedings of the 16th Design Automation Conference
Methods of compacting microprograms
Methods of compacting microprograms
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
Integrated scheduling and binding: a synthesis approach for design space exploration
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Automatic synthesis of microprogrammed control units from behavioral descriptions
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Verification of hardware descriptions by retargetable code generation
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Utilization of multiport memories in data path synthesis
DAC '93 Proceedings of the 30th international Design Automation Conference
A memory selection algorithm for high-performance pipelines
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Optimal register assignment to loops for embedded code generation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ISDL: an instruction set description language for retargetability
DAC '97 Proceedings of the 34th annual Design Automation Conference
Instruction selection, resource allocation, and scheduling in the AVIV retargetable code generator
DAC '98 Proceedings of the 35th annual Design Automation Conference
High-level synthesis: current status and future directions
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
A unified formal model of ISA and FSMD
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
A methodology for accurate performance evaluation in architecture exploration
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
The ITT VLSI design system: CAD integration in a multi-national environment
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
A new synthesis for the MIMOLA software system
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Synthesis of VLSI systems with the CAMAD design aid
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Allocation of FIFO structures in RTL data paths
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Quick piping: a fast, high-level model for describing processor pipelines
Proceedings of the joint conference on Languages, compilers and tools for embedded systems: software and compilers for embedded systems
Proceedings of the 39th annual Design Automation Conference
Readings in hardware/software co-design
Vertical Migration of Software Functions and Algorithms Using Enhanced Microsequencing
IEEE Transactions on Computers
A retargetable compiler for a high-level microprogramming language
MICRO 17 Proceedings of the 17th annual workshop on Microprogramming
High Level Synthesis from Sim-nML Processor Models
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Using Graph Models in Retargetable Optimizing Compilers for Microprocessors with VLIW Architectures
Cybernetics and Systems Analysis
Techniques for accurate performance evaluation in architecture exploration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A cycle-accurate compilation algorithm for custom pipelined datapaths
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Effective compiler generation by architecture description
Proceedings of the 2006 ACM SIGPLAN/SIGBED conference on Language, compilers, and tool support for embedded systems
Compiler generation from structural architecture descriptions
CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
Embedded DSP Processor Design: Application Specific Instruction Set Processors
Embedded DSP Processor Design: Application Specific Instruction Set Processors
| Hi-index | 0.00 |
The MIMOLA design method is a method for the design of digital processors from a very high-level bevavioral specification. A key feature of this method is the synthesis of a processor from a description of programs which are expected to be typical for the applications of that processor. Design cycles, in which the designer tries to improve automatically generated hardware structures, are supported by a retargetable microcode generator and by an utilization and performance analyzer. This paper describes the design method, available software tools and some applications.