Using Graph Models in Retargetable Optimizing Compilers for Microprocessors with VLIW Architectures

Authors:
A. E. Doroshenko;D. V. Ragozin
Affiliations:
Institute of Program Systems of NANU, Kiev, Ukraine dor@isofts.kiev.ua;Institute of Program Systems of NANU, Kiev, Ukraine dvragozin@yahoo.com
Venue:
Cybernetics and Systems Analysis
Year:
2003

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Abstract

A mathematical model of programs, which is based on the concept of a hierarchical graph, is described. The model is used in the retargetable optimizing compiler NVRK-2 for microprocessor architectures with irregular very long instruction words (VLIWs). A formal description of a microprocessor with such an architecture is proposed and issues of code generation and analysis of microprocessors with VLIWs extended by a collection of instructions for signal processing and multimedia application are discussed. The problem of the computational speedup of the architectures being considered is also discussed.