The ArchC architecture description language and tools

  • Authors:

  • Rodolfo Azevedo;Sandro Rigo;Marcus Bartholomeu;Guido Araujo;Cristiano Araujo;Edna Barros

  • Affiliations:

  • Computer Systems Laboratory, Institute of Computing, University of Campinas, Cidade Universitaria Zeferino Vaz, Campinas-SP, Brazil;Computer Systems Laboratory, Institute of Computing, University of Campinas, Cidade Universitaria Zeferino Vaz, Campinas-SP, Brazil;Computer Systems Laboratory, Institute of Computing, University of Campinas, Cidade Universitaria Zeferino Vaz, Campinas-SP, Brazil;Computer Systems Laboratory, Institute of Computing, University of Campinas, Cidade Universitaria Zeferino Vaz, Campinas-SP, Brazil;Computer Science Institute, Federal University of Pernambuco, Recife-PE, Brazil;Computer Science Institute, Federal University of Pernambuco, Recife-PE, Brazil

  • Venue:
  • International Journal of Parallel Programming
  • Year:
  • 2005

Quantified Score

Hi-index 0.00

Visualization

Abstract

This paper presents an architecture description language (ADL) called ArchC, which is an open-source SystemC-based language that is specialized for processor architecture description. Its main goal is to provide enough information, at the right level of abstraction, in order to allow users to explore and verify new architectures, by automatically generating software tools like simulators and coverification interfaces. ArchC's key features are a storage-based co-verification mechanism that automatically checks the consistency of a refined ArchC model against a reference (functional) description, memory hierarchy modeling capability, the possibility of integration with other SystemC IPs and the automatic generation of high-level SystemC simulators and assemblers. We have used ArchC to synthesize both functional and cycle-based simulators for the MIPS and Intel 8051 processors, as well as functional models of architectures like SPARC V8, TMS320C62x, XScale and PowerPC.