Shade: a fast instruction-set simulator for execution profiling
SIGMETRICS '94 Proceedings of the 1994 ACM SIGMETRICS conference on Measurement and modeling of computer systems
ISDL: an instruction set description language for retargetability
DAC '97 Proceedings of the 34th annual Design Automation Conference
Generation of software tools from processor descriptions for hardware/software codesign
DAC '97 Proceedings of the 34th annual Design Automation Conference
A retargetable, ultra-fast instruction set simulator
DATE '99 Proceedings of the conference on Design, automation and test in Europe
EXPRESSION: a language for architecture exploration through compiler/simulator retargetability
DATE '99 Proceedings of the conference on Design, automation and test in Europe
A generic tool set for application specific processor architectures
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
Facile: a language and compiler for high-performance processor simulators
Proceedings of the ACM SIGPLAN 2001 conference on Programming language design and implementation
A universal technique for fast and flexible instruction-set architecture simulation
Proceedings of the 39th annual Design Automation Conference
A retargetable micro-architecture simulator
Proceedings of the 40th annual Design Automation Conference
Instruction set compiled simulation: a technique for fast and flexible instruction set simulation
Proceedings of the 40th annual Design Automation Conference
Automated energy/performance macromodeling of embedded software
Proceedings of the 41st annual Design Automation Conference
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Generic Pipelined Processor Modeling and High Performance Cycle-Accurate Simulator Generation
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Methods for evaluating and covering the design space during early design development
Integration, the VLSI Journal
Hybrid simulation for embedded software energy estimation
Proceedings of the 42nd annual Design Automation Conference
Memory access optimizations in instruction-set simulators
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Proceedings of the 41st annual Design Automation Conference
The ArchC architecture description language and tools
International Journal of Parallel Programming
Fast cycle-approximate instruction set simulation
SCOPES '08 Proceedings of the 11th international workshop on Software & compilers for embedded systems
Processor Description Languages
Processor Description Languages
Precise simulation of interrupts using a rollback mechanism
Proceedings of th 12th International Workshop on Software and Compilers for Embedded Systems
A versatile generator of instruction set simulators and disassemblers
SPECTS'09 Proceedings of the 12th international conference on Symposium on Performance Evaluation of Computer & Telecommunication Systems
Statistical Performance Modeling in Functional Instruction Set Simulators
ACM Transactions on Embedded Computing Systems (TECS)
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Instruction-set architecture (ISA) simulators are an integral part of today's processor and software design process. While increasing complexity of the architectures demands high performance simulation, the increasing variety of available architectures makes retargetability a critical feature of an instruction-set simulator. Retargetability requires generic models while high performance demands target specific customizations. To address these contradictory requirements, we have developed a generic instruction model and a generic decode algorithm that facilitates easy and efficient retargetability of the ISA-simulator for a wide range of processor architectures such as RISC, CISC, VLIW and variable length instruction set processors. The instruction model is used to generate compact and easy to debug instruction descriptions that are very similar to that of architecture manual. These descriptions are used to generate high performance simulators. The generation of the simulator is completely separate from the simulation engine. Hence, we can incorporate any fast simulation technique in our retargetable framework without loosing performance. We illustrate the retargetability of our approach using two popular, yet different realistic architectures: the Sparc and the ARM.