MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Software performance estimation strategies in a system-level design tool
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
A universal technique for fast and flexible instruction-set architecture simulation
Proceedings of the 39th annual Design Automation Conference
Architecture Exploration for Embedded Processors with Lisa
Architecture Exploration for Embedded Processors with Lisa
Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques
Instruction set compiled simulation: a technique for fast and flexible instruction set simulation
Proceedings of the 40th annual Design Automation Conference
SMARTS: accelerating microarchitecture simulation via rigorous statistical sampling
Proceedings of the 30th annual international symposium on Computer architecture
A Data Analysis Method for Software Performance Prediction
Proceedings of the conference on Design, automation and test in Europe
An efficient retargetable framework for instruction-set simulation
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Link-time optimization of ARM binaries
Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Accurate software performance estimation using domain classification and neural networks
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
CODES+ISSS '04 Proceedings of the international conference on Hardware/Software Codesign and System Synthesis: 2004
IEEE Transactions on Pattern Analysis and Machine Intelligence
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Performance prediction based on inherent program similarity
Proceedings of the 15th international conference on Parallel architectures and compilation techniques
Accurate and efficient regression modeling for microarchitectural performance and power prediction
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
Fast compiler optimisation evaluation using code-feature based performance prediction
Proceedings of the 4th international conference on Computing frontiers
Fast cycle-approximate instruction set simulation
SCOPES '08 Proceedings of the 11th international workshop on Software & compilers for embedded systems
Hybrid-compiled simulation: An efficient technique for instruction-set architecture simulation
ACM Transactions on Embedded Computing Systems (TECS)
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
A compiler approach to performance prediction using empirical-based modeling
ICCS'03 Proceedings of the 2003 international conference on Computational science: PartIII
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Despite the recent progress in improving the speed of instruction-accurate simulators cycle-accurate simulation is still prohibitively slow for all but the most basic programs. In this article we present a statistical machine learning approach to performance estimation in fast, instruction accurate simulators and evaluate our methodology comprehensively against three popular embedded RISC processors and about 300 embedded applications. We show that our methodology is capable of providing accurate performance estimations with an average error of less than 3.9% while, on average, operating ≈ 14.5 times faster than cycle-accurate simulation.