A universal technique for fast and flexible instruction-set architecture simulation
Proceedings of the 39th annual Design Automation Conference
Implementation aspects of a SPARC V9 complete machine simulator
ACSC '02 Proceedings of the twenty-fifth Australasian conference on Computer science - Volume 4
Instruction set compiled simulation: a technique for fast and flexible instruction set simulation
Proceedings of the 40th annual Design Automation Conference
Describing instruction set processors using nML
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Processor Modeling for Hardware Software Codesign
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
Sleipnir-An Instruction-Level Simulator Generator
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
An efficient retargetable framework for instruction-set simulation
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Experimentation of WCET computation on both ends of automotive processor range
Proceedings of the 1st Workshop on Critical Automotive applications: Robustness & Safety
OTAWA: an open toolbox for adaptive WCET analysis
SEUS'10 Proceedings of the 8th IFIP WG 10.2 international conference on Software technologies for embedded and ubiquitous systems
Journal of Systems Architecture: the EUROMICRO Journal
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Instruction-set simulators (ISS) are more and more used in design space exploration and functional software testing. Furthermore, cycle-accurate simulators are often made of a functional coupled to a timing simulator. Research about ISS generators is not new but most often addresses only simple instruction sets (i.e. RISC). This paper describes techniques to ease the description of complex Instruction-Set Architectures and to increase simulation speed. They are integrated in a tool which generates libraries containing functions to disassemble (useful for testing), decode and simulate many different architectures like RISC, CISC, VLIW and is able to deal with variable-length instructions. We successfully generated and used ARM/thumb, HCS 12X, Tricore, Sharc, PPC simulators and experiments have been made on the x86 architecture.