MIPS RISC architectures
EEL: machine-independent executable editing
PLDI '95 Proceedings of the ACM SIGPLAN 1995 conference on Programming language design and implementation
Specifying representations of machine instructions
ACM Transactions on Programming Languages and Systems (TOPLAS)
The SimpleScalar tool set, version 2.0
ACM SIGARCH Computer Architecture News
LISA—machine description language for cycle-accurate models of programmable DSP architectures
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
The Designer's Guide to VHDL
The VERILOG Hardware Description Language
The VERILOG Hardware Description Language
Fast Simulation of Computer Architectures
Fast Simulation of Computer Architectures
MINT: A Front End for Efficient Simulation of Shared-Memory Multiprocessors
MASCOTS '94 Proceedings of the Second International Workshop on Modeling, Analysis, and Simulation On Computer and Telecommunication Systems
Automatic Generation of Microarchitecture Simulators
ICCL '98 Proceedings of the 1998 International Conference on Computer Languages
Extension Language Automation of Embedded System Debugging
Automated Software Engineering
A versatile generator of instruction set simulators and disassemblers
SPECTS'09 Proceedings of the 12th international conference on Symposium on Performance Evaluation of Computer & Telecommunication Systems
Automated generation of efficient instruction decoders for instruction set simulators
Proceedings of the International Conference on Computer-Aided Design
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Instruction-level simulators occupy a central role in the software development for embedded processors. They provide a convenient virtual platform for testing, debugging and optimizing code. They can be made available long before any hardware is available, and are not as awkward to work with as test/evaluation boards. However, many available instruction-level simulators are lacking in desired functionality. Moreover, instruction-level simulators suitable to the task are tedious to write from scratch.This paper presents the Sleipnir simulator generator, a convenient tool for writing instruction-level simulators. Sleipnir allows simulators for simple architectures to be generated with a minimum of overhead, yet allows sufficient micro-architectural detail to be expressed to generate cycle accurate simulators for most embedded processors. Sleipnir has been used to successfully generate fast instruction-level simulators for six different architectures, including a RISC processor, two microcontrollers and three DSPs.