Performance analysis of embedded software using implicit path enumeration
LCTES '95 Proceedings of the ACM SIGPLAN 1995 workshop on Languages, compilers, & tools for real-time systems
Bounding Pipeline and Instruction Cache Performance
IEEE Transactions on Computers
Worst Case Execution Time Analysis for a Processor withBranch Prediction
Real-Time Systems - Special issue on worst-case execution-time analysis
POPL '77 Proceedings of the 4th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Cache Behavior Prediction by Abstract Interpretation
SAS '96 Proceedings of the Third International Symposium on Static Analysis
A Worst Case Timing Analysis Technique for Optimized Programs
RTCSA '98 Proceedings of the 5th International Conference on Real-Time Computing Systems and Applications
Combining Abstract Interpretation and ILP for Microarchitecture Modelling and Program Path Analysis
RTSS '98 Proceedings of the IEEE Real-Time Systems Symposium
A Modular & Retargetable Framework for Tree-Based WCET Analysis
ECRTS '01 Proceedings of the 13th Euromicro Conference on Real-Time Systems
Writing Temporally Predictable Code
WORDS '02 Proceedings of the The Seventh IEEE International Workshop on Object-Oriented Real-Time Dependable Systems (WORDS 2002)
Efficient Integration of Bimodal Branch Prediction and Pipeline Analysis
RTCSA '05 Proceedings of the 11th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications
Modeling out-of-order processors for WCET analysis
Real-Time Systems
Worst case timing analysis of input dependent data cache behavior
ECRTS '06 Proceedings of the 18th Euromicro Conference on Real-Time Systems
WCET estimation for executables in the presence of data caches
EMSOFT '07 Proceedings of the 7th ACM & IEEE international conference on Embedded software
The worst-case execution-time problem—overview of methods and survey of tools
ACM Transactions on Embedded Computing Systems (TECS)
Static Loop Bound Analysis of C Programs Based on Flow Analysis and Abstract Interpretation
RTCSA '08 Proceedings of the 2008 14th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications
Improving the First-Miss Computation in Set-Associative Instruction Caches
ECRTS '08 Proceedings of the 2008 Euromicro Conference on Real-Time Systems
WCET Analysis of Multi-level Non-inclusive Set-Associative Instruction Caches
RTSS '08 Proceedings of the 2008 Real-Time Systems Symposium
Predictable dynamic instruction scratchpad for simultaneous multithreaded processors
Proceedings of the 9th workshop on MEmory performance: DEaling with Applications, systems and architecture
Hardware support for WCET analysis of hard real-time multicore systems
Proceedings of the 36th annual international symposium on Computer architecture
A versatile generator of instruction set simulators and disassemblers
SPECTS'09 Proceedings of the 12th international conference on Symposium on Performance Evaluation of Computer & Telecommunication Systems
Experimentation of WCET computation on both ends of automotive processor range
Proceedings of the 1st Workshop on Critical Automotive applications: Robustness & Safety
Deterministic execution model on COTS hardware
ARCS'12 Proceedings of the 25th international conference on Architecture of Computing Systems
FFX: a portable WCET annotation language
Proceedings of the 20th International Conference on Real-Time and Network Systems
Predictable two-level bus arbitration for heterogeneous task sets
ARCS'13 Proceedings of the 26th international conference on Architecture of Computing Systems
Time analysable synchronisation techniques for parallelised hard real-time applications
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
WCET squeezing: on-demand feasibility refinement for proven precise WCET-bounds
Proceedings of the 21st International conference on Real-Time Networks and Systems
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The analysis of worst-case execution times has become mandatory in the design of hard real-time systems: it is absolutely necessary to know an upper bound of the execution time of each task to determine a task schedule that insures that deadlines will all be met.The OTAWA toolbox presented in this paper has been designed to host algorithms resulting from research in the domain of WCET analysis so that they can be combined to compute tight WCET estimates. It features an abstraction layer that decouples the analyses from the target hardware and from the instruction set architecture, as well as a set of functionalities that facilitate the implementation of new approaches.