Design for Timing Predictability
Real-Time Systems
Code Analysis for Temporal Predictability
Real-Time Systems
Proceedings of the conference on Design, automation and test in Europe: Proceedings
WCET analysis for a Java processor
JTRES '06 Proceedings of the 4th international workshop on Java technologies for real-time and embedded systems
ACM SIGBED Review - Special issue: The work-in-progress (WIP) session of the RTSS 2005
A time-predictable VLIW processor and its compiler support
Real-Time Systems
A Java processor architecture for embedded real-time systems
Journal of Systems Architecture: the EUROMICRO Journal
SAFECOMP '08 Proceedings of the 27th international conference on Computer Safety, Reliability, and Security
An Operating System for a Time-Predictable Computing Node
SEUS '08 Proceedings of the 6th IFIP WG 10.2 international workshop on Software Technologies for Embedded and Ubiquitous Systems
Time-predictable computer architecture
EURASIP Journal on Embedded Systems - FPGA supercomputing platforms, architectures, and techniques for accelerating computationally complex algorithms
A Single-Path Chip-Multiprocessor System
SEUS '09 Proceedings of the 7th IFIP WG 10.2 International Workshop on Software Technologies for Embedded and Ubiquitous Systems
Worst-case execution time analysis for a Java processor
Software—Practice & Experience
OTAWA: an open toolbox for adaptive WCET analysis
SEUS'10 Proceedings of the 8th IFIP WG 10.2 international conference on Software technologies for embedded and ubiquitous systems
Specification and verification of side channel declassification
FAST'09 Proceedings of the 6th international conference on Formal Aspects in Security and Trust
Proceedings of the 15th European Conference on Pattern Languages of Programs
Compiling for time predictability
SAFECOMP'12 Proceedings of the 2012 international conference on Computer Safety, Reliability, and Security
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The Worst-Case Execution-Time Analysis (WCET Analysis) of program code for modern processors is a highly complex task. First, it involves path analysis, to identify and describe the possible execution paths through the code. Second, it models the worst-case timing of possible paths on the target hardware, where the characterization of the timing of sophisticated hardware features (e.g., instruction pipelines, caches, parallel execution units) and their interferences are non-trivial.This paper presents a programming paradigm that takes the complexity from WCET analysis. Program code written according to this paradigm only has a single execution path. Writing single-path code makes path analysis and thus WCET analysis trivial. The WCET of the single path is obtained by executing the code (necessarily on that single path) and logging the duration of this execution. To demonstrate that the single-path approach provides a universal solution to the WCET-analysis problem, the paper shows how every WCET-analyzable piece of code can be translated into single-path code.